A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes

Conference Paper (2019)
Author(s)

Jing Li (Student TU Delft, University of Electronic Science and Technology of China)

Zhao Chen (TU Delft - Electronic Instrumentation)

Mingliang Tan (TU Delft - Electronic Instrumentation)

Douwe Van Willigen (Student TU Delft)

Chao Chen (TU Delft - Transport and Logistics)

Zu Yao Chang (TU Delft - Electronic Instrumentation)

Emile Noothout (ImPhys/Acoustical Wavefield Imaging )

Nico De Jong (ImPhys/Acoustical Wavefield Imaging , Erasmus MC)

Martin Verweij (Erasmus MC, ImPhys/Acoustical Wavefield Imaging )

Michiel Pertijs (TU Delft - Electronic Instrumentation)

Research Group
Electronic Instrumentation
DOI related publication
https://doi.org/10.23919/VLSIC.2019.8778200
More Info
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Publication Year
2019
Language
English
Research Group
Electronic Instrumentation
Volume number
2019-June
Article number
8778200
Pages (from-to)
C220-C221
Publisher
IEEE
ISBN (electronic)
9784863487185
Event
33rd Symposium on VLSI Circuits, VLSI Circuits 2019 (2019-06-09 - 2019-06-14), Kyoto, Japan
Downloads counter
260

Abstract

This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μ m element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2 × 2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.

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