IN [1], there is a mistake in the timing diagram shown in Fig. 6. Switches S 1-S 4 are skipping some of the samples and the rate at which they are operating implies a TDM rate of 10 MHz, whereas (as described in [1]) this should be 20 MHz. In the updated Fig. 6, S 1-S 4 have been updated and a minor change has been made to the timing shown for switches Q₁ and Q₂, such that the correct TDM rate is indicated and no sample provided to the S/H stage via N1-N4 is skipped in the diagram. (Figure presented).

While medical imaging using ultrasound is an established field, technical advances are enabling a range of new-use cases and associated new ultrasound imaging devices. Examples include catheters capable of providing real-time 3D images to guide minimally invasive interventions and wearable devices for new monitoring and diagnostic applications. In contrast with conventional probes, which contain little or no electronics, these new devices need to become “smart”: integrated circuits need to be integrated into the probe to interface in a pitch-matched fashion with the many transducer elements (typically 1000+) needed for real-time 3D imaging. This chapter discusses the challenges associated with the design of such pitch-matched integrated circuits, focusing on strategies for channel-count reduction, beamforming, and digitization. The chapter includes a case study of a state-of-the-art catheter-based design for high-frame-rate 3D intracardiac imaging.

This article presents a pitch-matched transceiver application-specific integrated circuit (ASIC) for a wearable ultrasound device intended for transfontanelle ultrasonography, which includes element-level 20-V unipolar pulsers with transmit (TX) beamforming, and receive (RX) circuitry that combines eightfold multiplexing, four-channel micro-beamforming (?BF), and subgroup-level digitization to achieve an initial 32-fold channel-count reduction. The ?BF is based on passive boxcar integration, merged with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering (AAF) and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link, based on 16-level pulse-amplitude modulation, concatenates the outputs of four ADCs, providing an overall 128-fold channel-count reduction. A prototype transceiver ASIC was fabricated in a 180-nm BCD technology, and interfaces with a 2-D PZT transducer array of 16 × 16 elements with a pitch of 125 ?m and a center frequency of 9 MHz. The ASIC consumes 1.83 mW/element. The data link achieves an aggregate 3.84 Gb/s data rate with 3.3 pJ/bit energy efficiency. The ASIC's functionality has been demonstrated through electrical, acoustic, and imaging experiments.

This paper presents a pitch-matched transceiver ASIC integrated with a 2-D transducer array for a wearable ultrasound device for transfontanelle ultrasonography. The ASIC combines 8-fold multiplexing, 4-channel micro-beamforming (μ BF) and sub-array-level digitization to achieve a 128-fold channel-count reduction. The μ BF is based on passive boxcar integration and interfaces with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link concatenates outputs of four ADCs, leading to an aggregate 3.84 Gb/s data rate. Per channel, the RX circuit consumes 2.06 mW and occupies 0.05 mm2.

This article presents a low-power and small-area transceiver application-specific integrated circuit (ASIC) for 3-D trans-fontanelle ultrasonography. A novel micro-beamforming receiver architecture that employs current-mode summation and boxcar integration is used to realize delay-and-sum on an N -element sub-array using N× fewer capacitive memory elements than conventional micro-beamforming implementations, thus reducing the hardware overhead associated with the memory elements. The boxcar integration also obviates the need for explicit anti-aliasing filtering in the analog front end, thus further reducing die area. These features facilitate the use of micro-beamforming in smaller pitch applications, as demonstrated by a prototype transceiver ASIC employing micro-beamforming on sub-arrays of N=4 elements, targeting a wearable ultrasound device that monitors brain perfusion in preterm infants via the fontanel. To meet its strict spatial resolution requirements, a 10-MHz 100- μ m-pitch piezoelectric transducer array is employed, leading to a per-element die area > 2 × smaller than prior designs employing micro-beamforming.

The integration of 2D ultrasonic transducer arrays and pitch-matched ASICs has enabled the realization of various 3D ultrasound imaging devices in recent years [1]-[3]. As applications such as 3D intravascular ultrasonography, intra-cardiac echocardiography, and trans-fontanelle ultrasonography call for miniaturization and improved spatial resolution, higher-frequency transducers (>5MHz) with a correspondingly smaller array pitch (<150m) are needed. Such devices generally employ a large number of transducer elements, calling for channel-count reduction in the ASIC while meeting stringent restrictions on per-element power consumption and die area. Micro-beamforming (BF) is an effective way of reducing channel count by performing a delay-and-sum operation on the echo signals received within a sub-array [1]. However, prior BF implementations employ per-element capacitive memory to realize the delay [1], [2], making it increasingly difficult to apply BF in smaller-pitch arrays.

This article presents a compact analog front-end (AFE) circuit for ultrasound receivers with linear-in-dB continuous gain control for time-gain compensation (TGC). The AFE consists of two variable-gain stages, both of which employ a novel complementary current-steering network (CCSN) as the interpolator to realize continuously variable gain. The first stage is a trans-impedance amplifier (TIA) with a hardware-sharing inverter-based input stage to save power and area. The TIA's output couples capacitively to the second stage, which is a class-AB current amplifier (CA). The AFE is integrated into an application-specific integrated circuit (ASIC) in a 180-nm high-voltage BCD technology and assembled with a 100 μm-pitch PZT transducer array of 8 × 8 elements. Both electrical and acoustic measurements show that the AFE achieves a linear-in-dB gain error below ±0.4 dB within a 36-dB gain range, which is > 2 × better than the prior art. Per channel, the AFE occupies 0.025 mm2 area, consumes 0.8 mW power, and achieves an input-referred noise density of 1.31 pA/√Hz.