A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink

Conference Paper (2023)
Author(s)

P. Guo (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Z. Y. Chang (TU Delft - Electrical Engineering, Mathematics and Computer Science)

E. Noothout (TU Delft - Applied Sciences)

H. J. Vos (Erasmus MC, TU Delft - Applied Sciences)

J. G. Bosch (Erasmus MC)

N. De Jong (Erasmus MC, TU Delft - Applied Sciences)

M. D. Verweij (Erasmus MC, TU Delft - Applied Sciences, TU Delft - ImPhys/Medical Imaging)

M. A.P. Pertijs (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
Electronic Instrumentation
DOI related publication
https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185159 Final published version
More Info
expand_more
Publication Year
2023
Language
English
Research Group
Electronic Instrumentation
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Publisher
IEEE
ISBN (electronic)
9784863488069
Event
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (2023-06-11 - 2023-06-16), Kyoto, Japan
Downloads counter
446
Collections
Institutional Repository
Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Abstract

This paper presents a pitch-matched transceiver ASIC integrated with a 2-D transducer array for a wearable ultrasound device for transfontanelle ultrasonography. The ASIC combines 8-fold multiplexing, 4-channel micro-beamforming (μ BF) and sub-array-level digitization to achieve a 128-fold channel-count reduction. The μ BF is based on passive boxcar integration and interfaces with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link concatenates outputs of four ADCs, leading to an aggregate 3.84 Gb/s data rate. Per channel, the RX circuit consumes 2.06 mW and occupies 0.05 mm2.

Files

A_Pitch_Matched_Transceiver_AS... (pdf)
(pdf | 2.27 Mb)
- Embargo expired in 29-01-2024
License info not available