This article presents an application-specific integrated circuit (ASIC) for catheter-based 3-D ultrasound imaging probes. The pitch-matched design implements a comprehensive architecture with high-voltage (HV) transmitters, analog front ends, hybrid beamforming analog-To-digital converters (ADCs), and data transmission to the imaging system. To reduce the number of cables in the catheter while maintaining a small footprint per element, transmission (TX) beamforming is realized on the chip with a combination of a shift register (SR) and a row/column (R/C) approach. To explore an additional cable-count reduction in the receiver part of the design, a channel with a combination of time-division multiplexing (TDM), subarray beamforming, and multi-level pulse amplitude modulation (PAM) data transmission is also included. This achieves an 18-fold cable-count reduction and minimizes the power consumption in the catheter by a load modulation (LM) cable driver. It is further explored how common-mode interference can limit beamforming gain and a strategy to reduce its impact with local regulators is discussed. The chip was fabricated in TSMC 0.18-m HV BCD technology and a 2-D PZT transducer matrix of 16 × 18 elements with a pitch of 160 m and a center frequency of 6 MHz was manufactured on the chip. The system can generate all required TX patterns at up to 30 V, provides quick settling after the TX phase, and has an reception (RX) power consumption of only 1.12 mW/element. The functionality and operation of up to 1000 volumes/s have been demonstrated in electrical and acoustic imaging experiments.

In this article, an application-specific integrated circuit (ASIC) for 3-D, high-frame-rate ultrasound imaging probes is presented. The design is the first to combine element-level, high-voltage (HV) transmitters and analog front-ends, subarray beamforming, and in-probe digitization in a scalable fashion for catheter-based probes. The integration challenge is met by a hybrid analog-to-digital converter (ADC), combining an efficient charge-sharing successive approximation register (SAR) first stage and a compact single-slope (SS) second stage. Application in large ultrasound imaging arrays is facilitated by directly interfacing the ADC with a charge-domain subarray beamformer, locally calibrating interstage gain errors and generating the SAR reference using a power-efficient local reference generator. Additional hardware-sharing between neighboring channels ultimately leads to the lowest reported area and power consumption across miniature ultrasound probe ADCs. A pitch-matched design is further enabled by an efficient split between the core circuitry and a periphery block, the latter including a datalink performing clock data recovery (CDR) and time-division multiplexing (TDM), which leads to a 12-fold total channel count reduction. A prototype of $8{\times }9$ elements was fabricated in a TSMC 0.18- $\mu \text{m}$ HV BCD technology and a 2-D PZT transducer matrix with a pitch of $160 \mu \text{m}$ , and a center frequency of 6 MHz was manufactured on the chip. The imaging device operates at up to 1000 volumes/s, generates 65-V transmit pulses, and has a receive power consumption of only 1.23 mW/element. The functionality has been demonstrated electrically as well as in acoustic and imaging experiments.