The endeavor to emulate the extraordinary efficiency and adaptability inherent in the human brain via spike-based neuromorphic computing presents significant potential across a diverse array of applications. The attainment of this objective necessitates the translation of biological principles into artificial systems, a task that continues to pose a complex challenge requiring a profound comprehension of the mechanisms by which neural systems produce robust computational outcomes. This tutorial paper provides a comprehensive overview of the foundational concepts and emerging design trends in spike-based neuromorphic computing, covering advances from materials and circuits to hardware architectures and learning mechanisms. It begins with an examination of key aspects of brain biology and their influence on neuromorphic design, followed by a brief discussion of biologically plausible neuron and synapse models. The paper then defines the core principles and defining attributes of neuromorphic computing, highlighting the trade-offs and design choices underlying current implementations. Building on these foundations, it explores the critical properties of neuromorphic systems, surveys a variety of learning algorithms, and reviews hardware-level realizations of bioinspired neurons and synapses. Subsequent sections discuss state-of-the-art spiking neural network architectures, mapping and compilation strategies, and representative application domains. By providing this end-to-end perspective, the article aims to guide the development of future neuromorphic systems that more closely emulate brain efficiency, scalability, and resilience.

On-device learning at the edge enables low-latency, private personalization with improved long-term robustness and reduced maintenance costs. Yet, achieving scalable, low-power (LP) end-to-end on-chip learning, especially from real-world sequential data with a limited number of examples, is an open challenge. Indeed, accelerators supporting error backpropagation optimize for learning performance at the expense of inference efficiency, while simplified learning algorithms often fail to reach acceptable accuracy targets. In this work, we present Chameleon, leveraging three key contributions to solve these challenges: 1)aunified learning and inference architecture supports few-shot learning (FSL), continual learning (CL), and inference at only 0.5% area overhead to the inference logic; 2) long temporal dependencies are efficiently captured with temporal convolutional networks (TCNs), enabling the first demonstration of end-to-end on-chip FSL and CL on sequential data and inference on 16-kHz raw audio; and 3) a dual-mode, multiplier-free compute array allows either matching the power consumption of the state-of-the-art (SotA) inference-only keyword spotting (KWS) accelerators or enabling 4.3x higher peak GOPS. Fabricated in 40-nm CMOS, Chameleon sets new accuracy records on Omniglot for end-to-end on-chip FSL (96.8%, 5-way 1-shot and 98.8%, 5-way 5-shot) and CL (82.2% final accuracy for learning 250 classes with 10 shots), while maintaining an inference accuracy of 93.3% on the 12-class Google Speech Commands dataset at an extreme-edge power budget of 3.1 µW.

Neuromorphic computing shows promise for advancing computing efficiency and capabilities of AI applications using brain-inspired principles. However, the neuromorphic research field currently lacks standardized benchmarks, making it difficult to accurately measure technological advancements, compare performance with conventional methods, and identify promising future research directions. This article presents NeuroBench, a benchmark framework for neuromorphic algorithms and systems, which is collaboratively designed from an open community of researchers across industry and academia. NeuroBench introduces a common set of tools and systematic methodology for inclusive benchmark measurement, delivering an objective reference framework for quantifying neuromorphic approaches in both hardware-independent and hardware-dependent settings. For latest project updates, visit the project website (neurobench.ai).

Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) are promising solutions to enable μs-level inference latency and ultra-low energy in edge vision applications. Yet, their current lack of flexibility at both the circuit and system levels prevents their deployment in a wide range of real-life scenarios. In this work, we propose FlexSpIM, a novel digital CIM macro that supports arbitrary operand resolution and shape within a unified CIM storage for weights and membrane potentials. These circuit-level techniques enable a hybrid weight- and output-stationary dataflow at the system level to maximize operand reuse, thereby minimizing costly on- and off-chip data movements during the SNN execution. Measurement results of a fabricated FlexSpIM prototype in 40-nm CMOS demonstrate a 2× increase in 1-bit-normalized energy efficiency compared to prior fixed-precision digital CIM-based SNNs, while providing resolution reconfiguration with bitwise granularity. Our approach can save up to 90% energy in large-scale systems, while reaching a state-of-the-art classification accuracy of 95.8% on the IBM DVS gesture dataset.

With the rise of artificial intelligence, neural network simulations of biological neuron models are being explored to reduce the footprint of learning and inference in resource-constrained task scenarios. A mainstream type of such networks are spiking neural networks (SNNs) based on simplified Integrate and Fire models for which several hardware accelerators have emerged. Among them, the 'ReckOn' chip was introduced as a recurrent SNN allowing for both online training and execution of tasks based on arbitrary sensory modalities, demonstrated for vision, audition, and navigation. As a fully digital and opensource chip, we adapted ReckOn to be implemented on a Xilinx Multiprocessor System on Chip system (MPSoC), facilitating its deployment in embedded systems and increasing the setup flexibility. We present an overview of the system, and a Python framework to use it on a Pynq ZU platform. We validate the architecture and implementation in the new scenario of robotic arm control, and show how the simulated accuracy is preserved with a peak performance of 3.8M events processed per second.

The demand for low-power inference and training of deep neural networks (DNNs) on edge devices has intensified the need for algorithms that are both scalable and energy-efficient. While spiking neural networks (SNNs) allow for efficient inference by processing complex spatio-temporal dynamics in an event-driven fashion, training them on resource-constrained devices remains challenging due to the high computational and memory demands of conventional error backpropagation (BP)based approaches. In this work, we draw inspiration from biological mechanisms such as eligibility traces, spike-timing-dependent plasticity, and neural activity synchronization to introduce TESS, a temporally and spatially local learning rule for training SNNs. Our approach addresses both temporal and spatial credit assignments by relying solely on locally available signals within each neuron, thereby allowing computational and memory overheads to scale linearly with the number of neurons, independently of the number of time steps. Despite relying on local mechanisms, we demonstrate performance comparable to the backpropagation through time (BPTT) algorithm, within ∼ 1.4 accuracy points on challenging computer vision scenarios relevant at the edge, such as the IBM DVS Gesture dataset, CIFAR10-DVS, and temporal versions of CIFAR10, and CIFAR100. Being able to produce comparable performance to BPTT while keeping low time and memory complexity, TESS enables efficient and scalable on-device learning at the edge.

To give paralyzed people hope for a normal life, Brain Machine Interfaces (BMI) record signals from the motor cortex and a decoder translates these 'thoughts' to action. A high accuracy decoder is needed for a seamless user experience. At the same time it needs to be compact and low-power to support its integration in an implant to enable the compression required in wireless implantable BMIs. Hence, a model with a good trade-off between accuracy and resource requirement is desirable. In the IEEE BioCAS 2024 conference, we organized the first grand challenge on neural decoding for motor control. The evaluations were performed using the recently developed Neurobench software suite for benchmarking neuromorphic systems. There were two tracks -one preferring solutions with highest accuracy while the other gave weightage to the tradeoff between accuracy and implementation complexity. Out of the 10 teams registered for this event, the top 3 teams are invited to present their works in the IEEE BioCAS 2024.

Biomedical systems-on-chip (SoCs) for real-time monitoring of vital signs need to read out multiple recording channels in parallel and process them locally with low latency, at a low per-channel area and power consumption. To achieve this, event-driven SoCs that exploit the time-sparse nature of biosignals such as the electrocardiogram (ECG) have been proposed; they only process the signal when it shows activity. Such SoCs convert time-sparse biosignals into spike trains, on which spiking neural networks (SNNs) can perform event-driven signal classification. State-of-the-art event-driven SoCs, however, still suffer from poor area and power efficiency and use inflexible, hard-coded spike-encoding schemes. To improve on these challenges, this paper presents FREYA, an 8-channel event-driven SoC for end-to-end sensing of time-sparse biosignals. The proposed SoC consists of the following key contributions: 1) an 8-channel time-division-multiplexed level-crossing sampling (LCS) analog-to-spike converter (ASC) that encodes analog input signals into input spikes for an on-chip SNN; 2) an ASC spike-encoding algorithm that is fully programmable in resolution (4 to 8 bits) and conversion algorithm (offset and decay parameters); 3) an on-chip integrated, flexible SNN processor based on a programmable crossbar architecture, that allows for efficient event-driven processing, and that can be reconfigured towards multiple sensing applications; 4) a custom offline end-to-end training framework for the fast retraining of the spike-encoding algorithm and SNN architecture towards new applications or patient-dependent signal variations. A prototype IC has been fabricated in a 40nm CMOS technology. It has a per-channel active area of 0.023 mm2 (0.184 mm2 in total), a 7× improvement over the state of the art. For the use case of ECG-based QRS-labeling, a detection accuracy of 98.67% is achieved, while the system consumes 20.8μ W per channel and achieves a latency of only 80 ms, thus paving the way for multi-channel, high-fidelity, event-driven SoCs in biomedical applications.

While the human brain efficiently adapts to new tasks from a continuous stream of information, neural network models struggle to learn from sequential information without catastrophically forgetting previously learned tasks. This limitation presents a significant hurdle in deploying edge devices in real-world scenarios where information is presented in an inherently sequential manner. Active dendrites of pyramidal neurons play an important role in the brain's ability to learn new tasks incrementally. By exploiting key properties of time-to-first-spike (TTFS) encoding and leveraging its high sparsity, we present a novel spiking neural network (SNN) model enhanced with active dendrites. Our model can efficiently mitigate catastrophic forgetting in temporally-encoded SNNs, which we demonstrate with an end-of-training accuracy across tasks of 88.3% on the test set using the Split MNIST dataset. Furthermore, we provide a novel digital hardware architecture that paves the way for real-world deployment in edge devices. Using a Xilinx Zynq-7020 SoC FPGA, we demonstrate a 100-% match with our quantized software model, achieving an average inference time of 37.3 ms and an 80.0% accuracy.

Due to its intrinsic sparsity both in time and space, event-based data is optimally suited for edge-computing applications that require low power and low latency. Time varying signals encoded with this data representation are best processed with Spiking Neural Networks (SNN). In particular, recurrent SNNs (RSNNs) can solve temporal tasks using a relatively low number of parameters, and therefore support their hardware implementation in resource-constrained computing architectures. These premises propel the need of exploring the properties of these kinds of structures on low-power processing systems to test their limits both in terms of computational accuracy and resource consumption, without having to resort to full-custom implementations. In this work, we implemented an RSNN model on a low-end, resource-constrained ARM-Cortex-M4-based Micro Controller Unit (MCU). We trained it on a down-sampled version of the N-MNIST event-based dataset for digit recognition as an example to assess its performance in the inference phase. With an accuracy of 97.2%, the implementation has an average energy consumption as low as 4.1μJ and a worst-case computational time of 150.4μs per time-step with an operating frequency of 180 MHz, so the deployment of RSNNs on MCU devices is a feasible option for small image vision real-time tasks.

Level-crossing analog-To-digital converters (LC-ADCs) are neuromorphic, event-driven data converters that are gaining much attention for resource-constrained applications where intelligent sensing must be provided at the extreme edge, with tight energy and area budgets. LC-ADCs translate real-world analog signals (such as ECG, EEG, etc.) into sparse spiking signals, providing significant data bandwidth reduction and inducing savings of up to two orders of magnitude in area and energy consumption at the system level compared to the use of conventional ADCs. In addition, the spiking nature of LC-ADCs make their use a natural choice for ultra-low-power, event-driven spiking neural networks (SNNs). Still, the compressed nature of LC-ADC spiking signals can jeopardize the performance of downstream tasks such as signal classification accuracy, which is highly sensitive to the LC-ADC tuning parameters. In this paper, we explore the use of popular information criteria found in model selection theory for the tuning of the LC-ADC parameters. We experimentally demonstrate that information metrics such as the Bayesian, Akaike and corrected Akaike criteria can be used to tune the LC-ADC parameters in order to maximize downstream SNN classification accuracy. We conduct our experiments using both full-resolution weights and 4-bit quantized SNNs, on two different bio-signal classification tasks. We believe that our findings can accelerate the tuning of LC-ADC parameters without resorting to computationally-expensive grid searches that require many SNN training passes.

Recurrent neural networks trained with the backpropagation through time (BPTT) algorithm have led to astounding successes in various temporal tasks. However, BPTT introduces severe limitations, such as the requirement to propagate information backwards through time, the weight symmetry requirement, as well as update-locking in space and time. These problems become roadblocks for AI systems where online training capabilities are vital. Recently, researchers have developed biologically-inspired training algorithms, addressing a subset of those problems. In this work, we propose a novel learning algorithm called online spatio-temporal learning with target projection (OSTTP) that resolves all aforementioned issues of BPTT. In particular, OSTTP equips a network with the capability to simultaneously process and learn from new incoming data, alleviating the weight symmetry and update-locking problems. We evaluate OSTTP on two temporal tasks, showcasing competitive performance compared to BPTT. Moreover, we present a proof-of-concept implementation of OSTTP on a memristive neuromorphic hardware system, demonstrating its versatility and applicability to resource-constrained AI devices.