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S Narayanan
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Accurate synchronization of data samples is crucial for wireless sensor networks (WSNs) used for vibration monitoring and condition diagnostics. This paper describes two practical methods for achieving sample-level synchronization with better than 50 microsecond accuracy on battery-powered wireless MEMS accelerometer nodes. The first method uses a hardware-based real-time synchronization approach, where each sensor node has a 1.024 MHz clock which is synchronized through periodic interrupt pulses. The second method employs a software-based cross-correlation alignment to achieve precise synchronization after data acquisition, which is suitable for cases without accurate hardware clocks. Both methods are implemented using compact Bluetooth Low Energy (BLE) sensor nodes with off-the-shelf components. Experimental results on a shaker test platform confirm that synchronization within 50 µs is reliably achieved with both methods, demonstrating the suitability of these methods for industrial vibration monitoring applications.
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Accurate synchronization of data samples is crucial for wireless sensor networks (WSNs) used for vibration monitoring and condition diagnostics. This paper describes two practical methods for achieving sample-level synchronization with better than 50 microsecond accuracy on battery-powered wireless MEMS accelerometer nodes. The first method uses a hardware-based real-time synchronization approach, where each sensor node has a 1.024 MHz clock which is synchronized through periodic interrupt pulses. The second method employs a software-based cross-correlation alignment to achieve precise synchronization after data acquisition, which is suitable for cases without accurate hardware clocks. Both methods are implemented using compact Bluetooth Low Energy (BLE) sensor nodes with off-the-shelf components. Experimental results on a shaker test platform confirm that synchronization within 50 µs is reliably achieved with both methods, demonstrating the suitability of these methods for industrial vibration monitoring applications.
Conference paper
(2023)
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Shyam Narayanan, Matteo Cartiglia, Arianna Rubino, Charles Lego, Charlotte Frenkel, Giacomo Indiveri
Low-power event-based analog front-ends (AFE) are a crucial component required to build efficient end-to-end neuromorphic processing systems for edge computing. Although several neuromorphic chips have been developed for implementing spiking neural networks (SNNs) and solving a wide range of sensory processing tasks, there are only a few general-purpose analog front-end devices that can be used to convert analog sensory signals into spikes and interfaced to neuromorphic processors. In this work, we present a novel, highly configurable analog front-end chip, denoted as "SPAIC" (signal-to-spike converter for analog AI computation), that offers a general-purpose dual-mode analog signal-to-spike encoding with delta modulation and pulse frequency modulation, with tunable frequency bands. The ASIC is designed in a 180nm process. It supports and encodes a wide variety of signals spanning 4 orders of magnitude in frequency, and provides an event-based output that is compatible with existing neuromorphic processors. We validated the ASIC for its functions and present initial silicon measurement results characterizing the basic building blocks of the chip.
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Low-power event-based analog front-ends (AFE) are a crucial component required to build efficient end-to-end neuromorphic processing systems for edge computing. Although several neuromorphic chips have been developed for implementing spiking neural networks (SNNs) and solving a wide range of sensory processing tasks, there are only a few general-purpose analog front-end devices that can be used to convert analog sensory signals into spikes and interfaced to neuromorphic processors. In this work, we present a novel, highly configurable analog front-end chip, denoted as "SPAIC" (signal-to-spike converter for analog AI computation), that offers a general-purpose dual-mode analog signal-to-spike encoding with delta modulation and pulse frequency modulation, with tunable frequency bands. The ASIC is designed in a 180nm process. It supports and encodes a wide variety of signals spanning 4 orders of magnitude in frequency, and provides an event-based output that is compatible with existing neuromorphic processors. We validated the ASIC for its functions and present initial silicon measurement results characterizing the basic building blocks of the chip.