Imaging nanoscopic features with Scanning Electron Microscopes (SEMs) requires rapid specimen scanning with a low-energy electron beam. The electron detector is highly pixelated. Each pixel is interfaced with a high-precision, widebandwidth, low-noise readout integrated circuit (ROIC), to enable single-electron counting operation. This paper introduces an innovative power-efficient pixel readout frontend architecture, achieving a time resolution of 2.5 ns. The fabricated prototype in 40 nm CMOS process demonstrates better than 6 ppm electron detection precision. It consumes only 200 μ W, with an area of 150 μ m × 100 μ m.

Machine condition monitoring and predictive maintenance are crucial technologies in modern industrial settings. Wireless sensor networks (WSNs) are commonly used to gather machine data with high flexibility and minimal installation effort. However, traditional WSN approaches that periodically or selectively transmit raw data either lack predictive capability or consume excessive energy. Furthermore, conventional static Edge-AI models running entirely on sensor nodes struggle to adapt to dynamic and complex industrial conditions due to limited labelled failure data and unpredictable machine dynamics. In this paper, we propose and evaluate a hybrid edge-central AI architecture. In this approach, sensor nodes perform the feature extraction as the first layer of the AI model, while deeper adaptive model layers operate at the central base station. This approach reduces energy consumption by limiting radio transmissions and enabling the use of complex, adaptive AI models. We validate the proposed architecture by implementing a set of common features on a typical ARM Cortex-M4 microcontroller used in wireless sensor nodes. We target the architecture of our previously developed wireless 1kS/s (kilo-sample per second) accelerometer. Results demonstrate that these features can be computed in only 32.5 ms and consume 32.43 μW. This represents a significant energy saving compared to raw measurement transmission (686.4 μW), highlighting the effectiveness and feasibility of our hybrid approach for industrial monitoring.

Accurate registration of weak charge signals with a high event rate is the most challenging requirement of state-of-the-art detector readout frontends. This has given rise to the development of a wide variety of low-noise power-efficient readout frontends with a trend in achieving an ultra-small detection error and small silicon area occupation. This paper presents the methodology and experimental characterization of a state-of-the-art particle detection ROIC (readout integrated circuit) employing an active shaper after the frontend charge-sensitive amplifier (CSA), with: high time resolution (2.5 ns), low-noise, and very good power-efficiency, for registering charge signals between 140 aC and 200 aC, resulting from particles impinging in a silicon PIN detector. The small silicon area occupation of the readout electronic circuit allows a small detector area, which, in backside illumination/exposure mode, provides the opportunity for the pixelization of the total detector area with close to a 100 % fill factor. Experimental verification tests indicate that the proposed ROIC, designed in TSMC 40 nm MS/RF CMOS technology, operates with 3-sigma error rates between 1.8 ppm and 1.3 ppm (parts per million), with the above-mentioned charge signal range, provided that no more than one particle hits the detector surface in a 2.5 ns period of time. The power consumption is 0.37 mW.

Photodiodes based on the Boron on Silicon junction (B-Si) show excellent responsivity to DUV and VUV photons, radiation hardness, and impressive electrical characteristics. However, the proposed models describing the junction formation mechanism do not sufficiently predict the junction's properties. We analyze two previously proposed models: the ultra-shallow p-n junction model and the charge transfer heterojunction model. We additionally apply the Schottky-Mott theory, a semiconductor-metal heterojunction model. Both the commonalities and incompatibilities between these models are discussed.

This paper presents a thorough investigation and evaluation of readout Application-Specific Integrated Circuits (ASICs) tailored for Backscattered Electron (BSE) detection in electron microscopy. The study explores the architecture, operational principles, and performance assessment of integrating and electron counting systems utilized for signal processing in BSE detection. Evaluation of the count rate capability of the readout ASICs is undertaken under diverse conditions, considering variables such as BSE energy, discriminator threshold levels, and preamplifier characteristics. Detailed methodologies for experimental qualification, including test setups, trigger mechanisms, and count rate capability assessments, are outlined to ensure precise evaluation of the ASIC performance. The novel readout ASICs are compared by assessing their maximum output count rate capabilities. Furthermore, we propose strategies to enhance the output count rate by preventing preamplifier saturation, providing insights into the challenges and methods for achieving high-flux rate BSE detection. Experimental verifications validate the effectiveness of the proposed strategies and assessment methodologies in achieving high detection accuracy.

In modern nano-scale lithography, an essential role of the source, the illumination, and projection lenses is to deliver the precise amount of energy at a specific wavelength to the photoresist deposited on a wafer surface during exposure. Unfortunately, the source of the most advanced lithography processes may produce unwanted infrared components passing through the illumination and projection lenses and reaching the wafer surface. These infrared residues can cause local heating resulting in deformation of the optical elements and the exposed wafer, thus causing deterioration of the image quality. Some infrared spectrum components are in the band from 2 µm to 12 µm. An infrared detector that can measure only these spectral components of the exposure beam, without being affected by the much more powerful exposure spectral component, is helpful for optics diagnostic purposes and improving imaging quality. In this paper, an ultra-thin uncooled integrable-on-chip linear array infrared detector to measure the band of 2-12 µm infrared radiation is designed and fabricated based on the photovoltaic multiple junction heterostructure from VIGO Photonics, made of a HgCdTe narrow bandgap semiconductor. Features such as zero bias, low noise, and fast response, together with a wide active window, make the detector unique for use in the mid-infrared band. Besides lithography applications, the new detector can be useful in testing, inspection, and equipment using infrared sources such as: He-Ne lasers (0.6 to 4 µm), STEAM lasers (2 to 200 µm), CO2 lasers (5 to 11 µm), InGaAsP lasers (0.8 to 3 µm), and PbSnTe (3 to 20 µm) and PbSnSe (7 to 40 µm) lasers.

Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. In the state-of-The-Art systems, the trend is to design low-noise and low-power readout front-end electronics with a low detection error rate and small silicon area occupation. This paper presents the design of a high time resolution, low-noise, and power-efficient charge sensitive amplifier (CSA) in 40 nm CMOS technology. For every charge pulse of the detector, the CSA generates voltage signals with a peak amplitude of 30.6 mV, a rise time of 2.35 ns, and an equivalent noise charge (ENC) of 44e- with 0.14 mW power consumption.

This article presents the experimentally characterized performance of a low noise and wideband sensor readout integrated circuit (ROIC). The ROIC is designed to detect small amounts of charge generated by a silicon p-i-n detector as a result of particle detection, with very high time resolution and limited power consumption. The architecture of the ROIC permits the analog components of the particle readout to be designed with a reduced bandwidth by implementing the so-called intersymbol interference (ISI) cancellation technique, which improves the noise performance, while reducing the deterministic ISI-induced errors associated with the narrowband circuit; hence, a low error rate (ER) can be maintained. The readout is designed to detect 160 aC charge portions delivered randomly by the detector at a maximum of 4 × 108 events/s with a small average ER while consuming 2.85 mW. Detailed information about the ROIC designed in 65-nm CMOS technology, and the simulated performance, are already reported in a previous publication. This article aims to present the challenges related to the design of the test setup and the obtained experimental results with the first prototype of the ROIC, as well as to discuss the data acquisition process.

Most of the studies on narrow-band near-infrared detection reported so far are related to the 1.3μm and 1.55μm spectral windows. There is insufficient research work done on radiation detection in the narrow band around 1 μm wavelength, which is just outside the Si (0.95μ m) and GaAs (0.85μ m) effective cut-off spectral sensitivity. This paper presents a p+n Ge-on-Si detector with a customized large active window, employing the PureGaB technology, to detect radiation in a very narrow band around 1μ m. The advantages of the proposed detector are: (1) CMOS-compatibility and micro-spectroscopic capability; (2) low dark current and high photoresponsivity, compared to similar devices reported in the literature; (3) enhanced sensitivity to weak radiation by realizing an ultra-shallow and very thin depletion region. These detectors can be good candidates for measuring the YAG laser radiation and measuring stray radiation in photolithography.

Metal-Semiconductor (M/S) heterojunctions, better known as Schottky junctions play a crucial role in modern electronics. At present, the mechanisms behind the M/S junctions are still a subject of discussion. In this work, we investigate the interfaces between semiconducting crystalline Si and amorphous metallic indium, Si{0 0 1}/a-In and Si{1 1 1}/a-In using both ab initio molecular dynamics simulations and a Schottky-Mott approach. The simulations reveal the formation of a distinct border between the Si substrates and amorphous In at the interfaces. The In atoms adjacent to the interfaces exhibit atomic ordering. Charge transfer occurs from In to Si, forming c-Si^−q/a-In^+q charge barriers at the interfaces. This indicates that a crystalline p-Si/a-In heterojunction will have rectifying properties, which agrees with an analysis using the Schottky-Mott model which predicts a Schottky barrier height of 1.3 eV for crystalline p-Si/a-In using the calculated work function for a-In (3.82 eV). We further discuss the interfacial charge transfer, related hole-depletion regions in Si adjacent to the interfaces and the Schottky-Mott approximations.

The discovery of the extremely shallow amorphous boron-crystalline silicon heterojunction occurred during the development of highly sensitive, hard and robust detectors for low-penetration-depth ionizing radiation, such as ultraviolet photons and low-energy electrons (below 1 keV). For many years it was believed that the junction created by the chemical vapor deposition of amorphous boron on n-type crystalline silicon was a shallow p-n junction, although experimental results could not provide evidence for such a conclusion. Only recently, quantum-mechanics based modelling revealed the unique nature and the formation mechanism of this new junction. Here, we review the initiation and the history of understanding the a-B/c-Si interface (henceforth called the “boron-silicon junction”), as well as its importance for the microelectronics industry, followed by the scientific perception of the new junctions. Future developments and possible research directions are also discussed.

Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This article reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well as the widely used figure-of-merit (FoM). Interfaces based on period modulation feature simple circuitry, but their power efficiency at higher resolution deteriorates. Those employing Δ Σ modulation achieve high resolution with improved efficiency but require operational transconductance amplifiers that do not easily scale with process and supply voltage. Interfaces using successive approximation techniques feature mostly digital circuitry achieving good power efficiency at medium resolution. To achieve higher resolution, they can also be employed as the front-end in a hybrid architecture, where a back-end based on Δ Σ modulation or a voltage-controlled oscillator (VCO) performs a fine measurement on the front-end's residue, resulting in high resolution and excellent energy efficiency simultaneously.