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S. Nihtianov
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This thesis investigates three backend readout architectures for an event counting based scanning electron microscope (SEM) sensor formed by a matrix of detectors. A full adder tree, a critical adder tree, and a novel asynchronous pulse counter design are proposed. The full and critical adder trees are based on a Wallace tree, and provide synchronous summation of the detector outputs, with the critical adder tree reducing power by omitting higher order additions based on expected event rates. The pulse counter introduces a fundamentally different approach by converting asynchronous detector outputs into short pulses that propagate through a modified shift register. By matching latch to latch propagation delays to the pulse width, the design ensures that single pulses shift the register by one position, while overlapping pulses shift it by two. The resulting thermometer code is then synchronously encoded. This architecture eliminates the need for clock distribution to each detector, offering substantial power savings.
All three architectures were implemented and evaluated for a 16 × 16 detector matrix across event rates ranging from 0.01 to 4 total events per 2.5 ns. The full adder tree demonstrated reliable operation across all rates with a power consumption of 62 mW, dominated by clock distribution. The critical adder tree achieved similar reliability with a slightly lower power consumption of 60.5 mW. The pulse counter operated reliably up to 6.0×105 events per second while consuming only 1.26 mW, highlighting the efficiency of asynchronous processing.
A hierarchical, pipelined readout system was developed 128 × 128 detector matrix with a sampling period of 2.5 ns. Clock distribution was implemented using a balanced H tree, resulting in less than 100 ps skew from local device mismatches. The use of double data rate memory reduced the global clock frequency from 400 MHz to 200 MHz, reducing power consumption by 170 mW. A model of electron incidence across the detector matrix guided the selection of readout architectures for the first pipeline stage. Regions with higher expected event rates were implemented using the critical adder tree to minimize error, while lower rate regions used the pulse counter to minimize power. Subsequent pipeline stages were implemented using the critical adder tree.
The final mixed architecture system achieved a total power consumption of 0.9 W with an error rate of 232 ppm, compared to 4.3 W and zero errors for an implementation using only the critical adder tree. These results demonstrate a substantial and tunable trade off between power consumption and accuracy, validating the feasibility of low power, high rate readout for next generation SEM detector arrays. ...
All three architectures were implemented and evaluated for a 16 × 16 detector matrix across event rates ranging from 0.01 to 4 total events per 2.5 ns. The full adder tree demonstrated reliable operation across all rates with a power consumption of 62 mW, dominated by clock distribution. The critical adder tree achieved similar reliability with a slightly lower power consumption of 60.5 mW. The pulse counter operated reliably up to 6.0×105 events per second while consuming only 1.26 mW, highlighting the efficiency of asynchronous processing.
A hierarchical, pipelined readout system was developed 128 × 128 detector matrix with a sampling period of 2.5 ns. Clock distribution was implemented using a balanced H tree, resulting in less than 100 ps skew from local device mismatches. The use of double data rate memory reduced the global clock frequency from 400 MHz to 200 MHz, reducing power consumption by 170 mW. A model of electron incidence across the detector matrix guided the selection of readout architectures for the first pipeline stage. Regions with higher expected event rates were implemented using the critical adder tree to minimize error, while lower rate regions used the pulse counter to minimize power. Subsequent pipeline stages were implemented using the critical adder tree.
The final mixed architecture system achieved a total power consumption of 0.9 W with an error rate of 232 ppm, compared to 4.3 W and zero errors for an implementation using only the critical adder tree. These results demonstrate a substantial and tunable trade off between power consumption and accuracy, validating the feasibility of low power, high rate readout for next generation SEM detector arrays. ...
This thesis investigates three backend readout architectures for an event counting based scanning electron microscope (SEM) sensor formed by a matrix of detectors. A full adder tree, a critical adder tree, and a novel asynchronous pulse counter design are proposed. The full and critical adder trees are based on a Wallace tree, and provide synchronous summation of the detector outputs, with the critical adder tree reducing power by omitting higher order additions based on expected event rates. The pulse counter introduces a fundamentally different approach by converting asynchronous detector outputs into short pulses that propagate through a modified shift register. By matching latch to latch propagation delays to the pulse width, the design ensures that single pulses shift the register by one position, while overlapping pulses shift it by two. The resulting thermometer code is then synchronously encoded. This architecture eliminates the need for clock distribution to each detector, offering substantial power savings.
All three architectures were implemented and evaluated for a 16 × 16 detector matrix across event rates ranging from 0.01 to 4 total events per 2.5 ns. The full adder tree demonstrated reliable operation across all rates with a power consumption of 62 mW, dominated by clock distribution. The critical adder tree achieved similar reliability with a slightly lower power consumption of 60.5 mW. The pulse counter operated reliably up to 6.0×105 events per second while consuming only 1.26 mW, highlighting the efficiency of asynchronous processing.
A hierarchical, pipelined readout system was developed 128 × 128 detector matrix with a sampling period of 2.5 ns. Clock distribution was implemented using a balanced H tree, resulting in less than 100 ps skew from local device mismatches. The use of double data rate memory reduced the global clock frequency from 400 MHz to 200 MHz, reducing power consumption by 170 mW. A model of electron incidence across the detector matrix guided the selection of readout architectures for the first pipeline stage. Regions with higher expected event rates were implemented using the critical adder tree to minimize error, while lower rate regions used the pulse counter to minimize power. Subsequent pipeline stages were implemented using the critical adder tree.
The final mixed architecture system achieved a total power consumption of 0.9 W with an error rate of 232 ppm, compared to 4.3 W and zero errors for an implementation using only the critical adder tree. These results demonstrate a substantial and tunable trade off between power consumption and accuracy, validating the feasibility of low power, high rate readout for next generation SEM detector arrays.
All three architectures were implemented and evaluated for a 16 × 16 detector matrix across event rates ranging from 0.01 to 4 total events per 2.5 ns. The full adder tree demonstrated reliable operation across all rates with a power consumption of 62 mW, dominated by clock distribution. The critical adder tree achieved similar reliability with a slightly lower power consumption of 60.5 mW. The pulse counter operated reliably up to 6.0×105 events per second while consuming only 1.26 mW, highlighting the efficiency of asynchronous processing.
A hierarchical, pipelined readout system was developed 128 × 128 detector matrix with a sampling period of 2.5 ns. Clock distribution was implemented using a balanced H tree, resulting in less than 100 ps skew from local device mismatches. The use of double data rate memory reduced the global clock frequency from 400 MHz to 200 MHz, reducing power consumption by 170 mW. A model of electron incidence across the detector matrix guided the selection of readout architectures for the first pipeline stage. Regions with higher expected event rates were implemented using the critical adder tree to minimize error, while lower rate regions used the pulse counter to minimize power. Subsequent pipeline stages were implemented using the critical adder tree.
The final mixed architecture system achieved a total power consumption of 0.9 W with an error rate of 232 ppm, compared to 4.3 W and zero errors for an implementation using only the critical adder tree. These results demonstrate a substantial and tunable trade off between power consumption and accuracy, validating the feasibility of low power, high rate readout for next generation SEM detector arrays.
This Ph.D. dissertation focuses on designing high-precision readout frontends for low energy charge detection in scanning electron microscopy (SEM), achieving a time resolution of 2.5 ns, a detection error rate below 6 ppm, and power consumption under 400 μW. Novel techniques at both the system and circuit levels were developed to enhance operational accuracy and meet the target specifications. Two prototypes were presented and experimentally tested to demonstrate the effectiveness of these techniques.
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements. ...
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements. ...
This Ph.D. dissertation focuses on designing high-precision readout frontends for low energy charge detection in scanning electron microscopy (SEM), achieving a time resolution of 2.5 ns, a detection error rate below 6 ppm, and power consumption under 400 μW. Novel techniques at both the system and circuit levels were developed to enhance operational accuracy and meet the target specifications. Two prototypes were presented and experimentally tested to demonstrate the effectiveness of these techniques.
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements.
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements.
As a component of lithography machine, the wafer table plays an important role during wafer
exposure. The surface flatness condition of the WT will cause focus and overlay errors during
exposure and directly affect wafer distortion levels. This project takes advantage of global genetic algorithm to successfully develop a routing optimization design tool in MATLAB to deliver an efficient routing for genetic wafer fingerprints. ...
exposure. The surface flatness condition of the WT will cause focus and overlay errors during
exposure and directly affect wafer distortion levels. This project takes advantage of global genetic algorithm to successfully develop a routing optimization design tool in MATLAB to deliver an efficient routing for genetic wafer fingerprints. ...
As a component of lithography machine, the wafer table plays an important role during wafer
exposure. The surface flatness condition of the WT will cause focus and overlay errors during
exposure and directly affect wafer distortion levels. This project takes advantage of global genetic algorithm to successfully develop a routing optimization design tool in MATLAB to deliver an efficient routing for genetic wafer fingerprints.
exposure. The surface flatness condition of the WT will cause focus and overlay errors during
exposure and directly affect wafer distortion levels. This project takes advantage of global genetic algorithm to successfully develop a routing optimization design tool in MATLAB to deliver an efficient routing for genetic wafer fingerprints.
This thesis proposes the design of a new type of read-out circuit for a PIN diode used in Scanning Electron Microscope (SEM) applications. The circuit operates in voltage mode (with high input impedance), which offers significant power-saving advantages over the traditionally used current mode (with low input impedance). The final read-out circuit can detect the incoming charge of ∼1000e− with a temporal resolution of 2.5 ns at a frequency of 400 MHz. Post-layout simulation
results indicate a promising reduction in power consumption to 188 µW per pixel.
At the core of the read-out circuit is a dynamic comparator. The dynamic comparator is designed to operate with low noise at high frequencies while still having a low power consumption. The final comparator has a delay of 240 ps and 140 µV of input-referred noise while consuming 71 fJ/conversion.
The comparator has active offset compensation which reduces the offset from 1σ = 5.87 mV to 1σ = 172 µV in 100 ns.
The threshold for the dynamic comparator is created by inserting a small charge of 500e− on the detector, whose polarity is opposite to that of the signal. By creating the threshold as a charge, the ratio between the threshold and the signal is made independent of the detector capacitance.
The final pixel is implemented in 40 nm TSMC CMOS technology and occupies an area of 80 µm x 98 µm which includes additional circuits designed to measure and quantify the performance of the pixel. The measurement setup is designed but unfortunately, due to delays in the chip delivery, no measurements could be performed ...
results indicate a promising reduction in power consumption to 188 µW per pixel.
At the core of the read-out circuit is a dynamic comparator. The dynamic comparator is designed to operate with low noise at high frequencies while still having a low power consumption. The final comparator has a delay of 240 ps and 140 µV of input-referred noise while consuming 71 fJ/conversion.
The comparator has active offset compensation which reduces the offset from 1σ = 5.87 mV to 1σ = 172 µV in 100 ns.
The threshold for the dynamic comparator is created by inserting a small charge of 500e− on the detector, whose polarity is opposite to that of the signal. By creating the threshold as a charge, the ratio between the threshold and the signal is made independent of the detector capacitance.
The final pixel is implemented in 40 nm TSMC CMOS technology and occupies an area of 80 µm x 98 µm which includes additional circuits designed to measure and quantify the performance of the pixel. The measurement setup is designed but unfortunately, due to delays in the chip delivery, no measurements could be performed ...
This thesis proposes the design of a new type of read-out circuit for a PIN diode used in Scanning Electron Microscope (SEM) applications. The circuit operates in voltage mode (with high input impedance), which offers significant power-saving advantages over the traditionally used current mode (with low input impedance). The final read-out circuit can detect the incoming charge of ∼1000e− with a temporal resolution of 2.5 ns at a frequency of 400 MHz. Post-layout simulation
results indicate a promising reduction in power consumption to 188 µW per pixel.
At the core of the read-out circuit is a dynamic comparator. The dynamic comparator is designed to operate with low noise at high frequencies while still having a low power consumption. The final comparator has a delay of 240 ps and 140 µV of input-referred noise while consuming 71 fJ/conversion.
The comparator has active offset compensation which reduces the offset from 1σ = 5.87 mV to 1σ = 172 µV in 100 ns.
The threshold for the dynamic comparator is created by inserting a small charge of 500e− on the detector, whose polarity is opposite to that of the signal. By creating the threshold as a charge, the ratio between the threshold and the signal is made independent of the detector capacitance.
The final pixel is implemented in 40 nm TSMC CMOS technology and occupies an area of 80 µm x 98 µm which includes additional circuits designed to measure and quantify the performance of the pixel. The measurement setup is designed but unfortunately, due to delays in the chip delivery, no measurements could be performed
results indicate a promising reduction in power consumption to 188 µW per pixel.
At the core of the read-out circuit is a dynamic comparator. The dynamic comparator is designed to operate with low noise at high frequencies while still having a low power consumption. The final comparator has a delay of 240 ps and 140 µV of input-referred noise while consuming 71 fJ/conversion.
The comparator has active offset compensation which reduces the offset from 1σ = 5.87 mV to 1σ = 172 µV in 100 ns.
The threshold for the dynamic comparator is created by inserting a small charge of 500e− on the detector, whose polarity is opposite to that of the signal. By creating the threshold as a charge, the ratio between the threshold and the signal is made independent of the detector capacitance.
The final pixel is implemented in 40 nm TSMC CMOS technology and occupies an area of 80 µm x 98 µm which includes additional circuits designed to measure and quantify the performance of the pixel. The measurement setup is designed but unfortunately, due to delays in the chip delivery, no measurements could be performed
Pixel charge detectors are responsible for counting the number of collected electrons and converting it into an electrical signal. The proposed charge detector pixel readout integrated circuit (ROIC), implemented in 40nm TSMC technology, should be able to detect an amount of charge as low as 160aC, with a high time resolution of 2.5ns, using limited power consumption and area occupation. The discriminator, as the ROIC's last block, should distinguish the analog information of the previous block called “signal shaper”, from a certain noise level, and convert it into 1-bit binary code. The mode of operation is named as an event counting.
In this thesis, two versions of the discriminator are studied and compared: with an active and passive shaper (filter). The goal is to find the optimal solution with respect to performance and power efficiency. The discriminator with an active filter (which provides an output pulse with an amplitude of 225mV and power consumption of 170μW, achieves an offset of 5mV and a noise voltage of 290μVrms referred to the input, and consumes a power of 36μW. Its speed performance and temperature stability have been experimentally verified. The discriminator with a passive shaper (which consumes no power) can detect an input signal with 10mV amplitude, with 240μV input noise, and a power consumption of 88μW. Its performance is partly tested through the post-layout simulation.
The achieved SNR with the active filter is 14.6, and the passive filter is 15.1. Both solutions (discriminator for active and passive filter) demonstrate an acceptable SNR. The solution with a passive filter provides a better overall power efficiency but cannot detect incoming events during the calibration period which lasts 10ns and occurs every 90μs. ...
In this thesis, two versions of the discriminator are studied and compared: with an active and passive shaper (filter). The goal is to find the optimal solution with respect to performance and power efficiency. The discriminator with an active filter (which provides an output pulse with an amplitude of 225mV and power consumption of 170μW, achieves an offset of 5mV and a noise voltage of 290μVrms referred to the input, and consumes a power of 36μW. Its speed performance and temperature stability have been experimentally verified. The discriminator with a passive shaper (which consumes no power) can detect an input signal with 10mV amplitude, with 240μV input noise, and a power consumption of 88μW. Its performance is partly tested through the post-layout simulation.
The achieved SNR with the active filter is 14.6, and the passive filter is 15.1. Both solutions (discriminator for active and passive filter) demonstrate an acceptable SNR. The solution with a passive filter provides a better overall power efficiency but cannot detect incoming events during the calibration period which lasts 10ns and occurs every 90μs. ...
Pixel charge detectors are responsible for counting the number of collected electrons and converting it into an electrical signal. The proposed charge detector pixel readout integrated circuit (ROIC), implemented in 40nm TSMC technology, should be able to detect an amount of charge as low as 160aC, with a high time resolution of 2.5ns, using limited power consumption and area occupation. The discriminator, as the ROIC's last block, should distinguish the analog information of the previous block called “signal shaper”, from a certain noise level, and convert it into 1-bit binary code. The mode of operation is named as an event counting.
In this thesis, two versions of the discriminator are studied and compared: with an active and passive shaper (filter). The goal is to find the optimal solution with respect to performance and power efficiency. The discriminator with an active filter (which provides an output pulse with an amplitude of 225mV and power consumption of 170μW, achieves an offset of 5mV and a noise voltage of 290μVrms referred to the input, and consumes a power of 36μW. Its speed performance and temperature stability have been experimentally verified. The discriminator with a passive shaper (which consumes no power) can detect an input signal with 10mV amplitude, with 240μV input noise, and a power consumption of 88μW. Its performance is partly tested through the post-layout simulation.
The achieved SNR with the active filter is 14.6, and the passive filter is 15.1. Both solutions (discriminator for active and passive filter) demonstrate an acceptable SNR. The solution with a passive filter provides a better overall power efficiency but cannot detect incoming events during the calibration period which lasts 10ns and occurs every 90μs.
In this thesis, two versions of the discriminator are studied and compared: with an active and passive shaper (filter). The goal is to find the optimal solution with respect to performance and power efficiency. The discriminator with an active filter (which provides an output pulse with an amplitude of 225mV and power consumption of 170μW, achieves an offset of 5mV and a noise voltage of 290μVrms referred to the input, and consumes a power of 36μW. Its speed performance and temperature stability have been experimentally verified. The discriminator with a passive shaper (which consumes no power) can detect an input signal with 10mV amplitude, with 240μV input noise, and a power consumption of 88μW. Its performance is partly tested through the post-layout simulation.
The achieved SNR with the active filter is 14.6, and the passive filter is 15.1. Both solutions (discriminator for active and passive filter) demonstrate an acceptable SNR. The solution with a passive filter provides a better overall power efficiency but cannot detect incoming events during the calibration period which lasts 10ns and occurs every 90μs.
This thesis focuses on the design of a high input impedance sensor readout system based on a continuous-time sigma-delta modulator with finite-impulse-response digital-to-analog converter feedback.
Both the system-level and circuit-level design techniques of this system are investigated. The concept and design methods of finite-impulse-response digital-to-analog converters are introduced. The first integrator with source degeneration resistors and an input Gm-boosting cell is designed to achieve high input impedance and linearity. Both simulation and post-layout simulation results confirm the expected effective number of bits of 15 bits in the readout performance. The design is fabricated in a standard 180nm CMOS technology. ...
Both the system-level and circuit-level design techniques of this system are investigated. The concept and design methods of finite-impulse-response digital-to-analog converters are introduced. The first integrator with source degeneration resistors and an input Gm-boosting cell is designed to achieve high input impedance and linearity. Both simulation and post-layout simulation results confirm the expected effective number of bits of 15 bits in the readout performance. The design is fabricated in a standard 180nm CMOS technology. ...
This thesis focuses on the design of a high input impedance sensor readout system based on a continuous-time sigma-delta modulator with finite-impulse-response digital-to-analog converter feedback.
Both the system-level and circuit-level design techniques of this system are investigated. The concept and design methods of finite-impulse-response digital-to-analog converters are introduced. The first integrator with source degeneration resistors and an input Gm-boosting cell is designed to achieve high input impedance and linearity. Both simulation and post-layout simulation results confirm the expected effective number of bits of 15 bits in the readout performance. The design is fabricated in a standard 180nm CMOS technology.
Both the system-level and circuit-level design techniques of this system are investigated. The concept and design methods of finite-impulse-response digital-to-analog converters are introduced. The first integrator with source degeneration resistors and an input Gm-boosting cell is designed to achieve high input impedance and linearity. Both simulation and post-layout simulation results confirm the expected effective number of bits of 15 bits in the readout performance. The design is fabricated in a standard 180nm CMOS technology.
Single Electron Readout Circuit
SERCuit
Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. State-of-the-art imaging systems demand the detection of small amounts of charge with small time-resolution and limited power consumption, creating an implementation dead-end for the typical readout topology. In this thesis, a particle detection readout based on an intersymbol interference cancellation scheme is introduced to address this issue. Evaluated in post-layout simulations, the proposed architecture can detect generated charge as small as 160 aC with 97.8 % certainty. The readout can operate with event-rates up to 400 MEvent/s while only consuming
2.85 mW of power. ...
2.85 mW of power. ...
Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. State-of-the-art imaging systems demand the detection of small amounts of charge with small time-resolution and limited power consumption, creating an implementation dead-end for the typical readout topology. In this thesis, a particle detection readout based on an intersymbol interference cancellation scheme is introduced to address this issue. Evaluated in post-layout simulations, the proposed architecture can detect generated charge as small as 160 aC with 97.8 % certainty. The readout can operate with event-rates up to 400 MEvent/s while only consuming
2.85 mW of power.
2.85 mW of power.
Wireless sensor networks play a vital role in major technological developments. The success of such networks depend on the quality and reliability of data acquisition. Despite a lot of research involving network clock synchronization, the area of synchronous sampling has not been dealt in much detail. This thesis aims at studying and implementing synchronization at the sensor level on wireless accelerometer sensors. The designated application for this thesis involves machine condition monitoring using accelerometer sensors that requires high synchronization accuracy between the samples. Two approaches are presented to obtain synchronous sampling, namely: real-time and subsequent synchronization. The sensor nodes designed with commercially-off-the-shelf components are used for the implementation of the two methods. The embedded software was developed as a platform to realize the proposed synchronous data acquisition techniques. The real-time synchronization uses a software solution and provides an interrupt-based triggering to align the sampling instant of the sensors. An external reliable clock source is required for the accelerometer to implement this technique. The signal propagation delay were minimized by employing interrupts whenever possible. In subsequent synchronization, the samples are collected asynchronously by the sensor nodes. Each sample from the sensor is assigned a timestamp according to its local clock. As a post-process, the time shift between the samples collected by the sensor nodes are estimated and realigned using cross-correlation, interpolation and re-sampling. The subsequent synchronization technique can be used when real-time network synchronization is not possible. The testing environment was designed to emulate the real application. A mechanical shaker was used to provide controlled input signals to the sensors in order to synchronously reconstruct the signals in time-domain.
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Wireless sensor networks play a vital role in major technological developments. The success of such networks depend on the quality and reliability of data acquisition. Despite a lot of research involving network clock synchronization, the area of synchronous sampling has not been dealt in much detail. This thesis aims at studying and implementing synchronization at the sensor level on wireless accelerometer sensors. The designated application for this thesis involves machine condition monitoring using accelerometer sensors that requires high synchronization accuracy between the samples. Two approaches are presented to obtain synchronous sampling, namely: real-time and subsequent synchronization. The sensor nodes designed with commercially-off-the-shelf components are used for the implementation of the two methods. The embedded software was developed as a platform to realize the proposed synchronous data acquisition techniques. The real-time synchronization uses a software solution and provides an interrupt-based triggering to align the sampling instant of the sensors. An external reliable clock source is required for the accelerometer to implement this technique. The signal propagation delay were minimized by employing interrupts whenever possible. In subsequent synchronization, the samples are collected asynchronously by the sensor nodes. Each sample from the sensor is assigned a timestamp according to its local clock. As a post-process, the time shift between the samples collected by the sensor nodes are estimated and realigned using cross-correlation, interpolation and re-sampling. The subsequent synchronization technique can be used when real-time network synchronization is not possible. The testing environment was designed to emulate the real application. A mechanical shaker was used to provide controlled input signals to the sensors in order to synchronously reconstruct the signals in time-domain.
The availability of photolithography machines is key in the semiconductor industry, as downtime generally incurs in immense economic loss. Time to market is also very important for suppliers of photolithography systems, such as ASML. Photolithography machines include numerous measurement systems that are frequently used for qualification and troubleshooting, most of which are required during normal operation. Due to increased costs and complexity, it would not be practical to include dedicated sensors for every machine performance parameter relevant for diagnosis, therefore many parameters regarded as non-critical are not monitored. However, in some cases the information about the behaviour of these parameters can be very valuable to find the root cause of a failure or defect promptly. In these cases, a Wireless Sensor Network (WSN) would allow for a temporary installation of a measurement system to monitor such parameters.
This work presents the design of a WSN for monitoring the dynamics performance of the WaferHandler (WH), which is one of the major subsystems of a photolithography machine. The scope of the project includes:
• The selection of a radio technology on which the network is based on.
• The hardware design of a wireless sensor node for measuring acceleration, based on commercial off-the-shelf (COTS) components.
• The identification and firmware implementation of key principles in which the communication protocol should be based on according to the requirements of the application.
• The estimation of the power consumption and lifetime of the network.
• The design and execution of experiments to assess the reliability of the proposed solution.
Among the requirements of the system, the size of the sensor nodes, the network synchronization accuracy, and the maximum power dissipation stand out as the main challenges. As the available space inside the WH is very scarce, the sensor nodes must have a compact form factor to fit in the locations where they are meant to be installed. The reliability of the system is greatly determined by its capacity to remain synchronized with relatively high accuracy during a measurement. This can be difficult to achieve in a harsh environment such as the inside of a machine, where interference and signal fading are expected to recurrently cause the loss of packets used for network synchronization.Packet re-transmission should not be abused to alleviate the problem, as the sensor nodes are required to operate in vacuum and overheating can become a problem. ...
This work presents the design of a WSN for monitoring the dynamics performance of the WaferHandler (WH), which is one of the major subsystems of a photolithography machine. The scope of the project includes:
• The selection of a radio technology on which the network is based on.
• The hardware design of a wireless sensor node for measuring acceleration, based on commercial off-the-shelf (COTS) components.
• The identification and firmware implementation of key principles in which the communication protocol should be based on according to the requirements of the application.
• The estimation of the power consumption and lifetime of the network.
• The design and execution of experiments to assess the reliability of the proposed solution.
Among the requirements of the system, the size of the sensor nodes, the network synchronization accuracy, and the maximum power dissipation stand out as the main challenges. As the available space inside the WH is very scarce, the sensor nodes must have a compact form factor to fit in the locations where they are meant to be installed. The reliability of the system is greatly determined by its capacity to remain synchronized with relatively high accuracy during a measurement. This can be difficult to achieve in a harsh environment such as the inside of a machine, where interference and signal fading are expected to recurrently cause the loss of packets used for network synchronization.Packet re-transmission should not be abused to alleviate the problem, as the sensor nodes are required to operate in vacuum and overheating can become a problem. ...
The availability of photolithography machines is key in the semiconductor industry, as downtime generally incurs in immense economic loss. Time to market is also very important for suppliers of photolithography systems, such as ASML. Photolithography machines include numerous measurement systems that are frequently used for qualification and troubleshooting, most of which are required during normal operation. Due to increased costs and complexity, it would not be practical to include dedicated sensors for every machine performance parameter relevant for diagnosis, therefore many parameters regarded as non-critical are not monitored. However, in some cases the information about the behaviour of these parameters can be very valuable to find the root cause of a failure or defect promptly. In these cases, a Wireless Sensor Network (WSN) would allow for a temporary installation of a measurement system to monitor such parameters.
This work presents the design of a WSN for monitoring the dynamics performance of the WaferHandler (WH), which is one of the major subsystems of a photolithography machine. The scope of the project includes:
• The selection of a radio technology on which the network is based on.
• The hardware design of a wireless sensor node for measuring acceleration, based on commercial off-the-shelf (COTS) components.
• The identification and firmware implementation of key principles in which the communication protocol should be based on according to the requirements of the application.
• The estimation of the power consumption and lifetime of the network.
• The design and execution of experiments to assess the reliability of the proposed solution.
Among the requirements of the system, the size of the sensor nodes, the network synchronization accuracy, and the maximum power dissipation stand out as the main challenges. As the available space inside the WH is very scarce, the sensor nodes must have a compact form factor to fit in the locations where they are meant to be installed. The reliability of the system is greatly determined by its capacity to remain synchronized with relatively high accuracy during a measurement. This can be difficult to achieve in a harsh environment such as the inside of a machine, where interference and signal fading are expected to recurrently cause the loss of packets used for network synchronization.Packet re-transmission should not be abused to alleviate the problem, as the sensor nodes are required to operate in vacuum and overheating can become a problem.
This work presents the design of a WSN for monitoring the dynamics performance of the WaferHandler (WH), which is one of the major subsystems of a photolithography machine. The scope of the project includes:
• The selection of a radio technology on which the network is based on.
• The hardware design of a wireless sensor node for measuring acceleration, based on commercial off-the-shelf (COTS) components.
• The identification and firmware implementation of key principles in which the communication protocol should be based on according to the requirements of the application.
• The estimation of the power consumption and lifetime of the network.
• The design and execution of experiments to assess the reliability of the proposed solution.
Among the requirements of the system, the size of the sensor nodes, the network synchronization accuracy, and the maximum power dissipation stand out as the main challenges. As the available space inside the WH is very scarce, the sensor nodes must have a compact form factor to fit in the locations where they are meant to be installed. The reliability of the system is greatly determined by its capacity to remain synchronized with relatively high accuracy during a measurement. This can be difficult to achieve in a harsh environment such as the inside of a machine, where interference and signal fading are expected to recurrently cause the loss of packets used for network synchronization.Packet re-transmission should not be abused to alleviate the problem, as the sensor nodes are required to operate in vacuum and overheating can become a problem.
This Ph.D. dissertation describes the design and realization of energy efficient readout integrated circuits (ROICs), that have an input referred noise density < 5 nV/√Hz and a linearity of < 30 ppm, as required by Wheatstone bridge sensors used in precision mechatronic systems. Novel techniques were developed, at both the system-level and circuit-level, to improve the ROIC’s energy-efficiency, while preserving its stability and precision. Two prototypes are presented, each with bestin- class energy efficiency, to demonstrate the effectiveness of the proposed techniques.
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This Ph.D. dissertation describes the design and realization of energy efficient readout integrated circuits (ROICs), that have an input referred noise density < 5 nV/√Hz and a linearity of < 30 ppm, as required by Wheatstone bridge sensors used in precision mechatronic systems. Novel techniques were developed, at both the system-level and circuit-level, to improve the ROIC’s energy-efficiency, while preserving its stability and precision. Two prototypes are presented, each with bestin- class energy efficiency, to demonstrate the effectiveness of the proposed techniques.
This thesis presents a capacitive sensing technique which is suitable for measuring small displacements with one floating target electrode. A capacitive sensor interface, which does not require electrical contact with the target, while demonstrating performance comparable with the state-of-the-art, is proposed. The designed prototype is intended for displacement measurement with a measurement range from 10 µm to 100 µm, and a resolution better than 3 nm.
The proposed design implants the sensor capacitor into the input branch of a capacitance-to-digital converter (CDC), which results in a simpler system that saves power and reduces the error sources.
The CDC is taped out in the TSMC 0.18 µm CMOS process with Vdd = 1.8 V. The total chip area is 2.3 mm2 of which 0.5 mm2 is occupied by the CDC. In frequency range from DC to 2 kHz, the resolution of the CDC is thermal noise limited, whereas the quantization noise is shaped to higher frequency. After applying a low-pass digital filter with a bandwidth of 1 kHz, the dynamic range is better than 15 bits, corresponding to 3 nm displacement resolution. ...
The proposed design implants the sensor capacitor into the input branch of a capacitance-to-digital converter (CDC), which results in a simpler system that saves power and reduces the error sources.
The CDC is taped out in the TSMC 0.18 µm CMOS process with Vdd = 1.8 V. The total chip area is 2.3 mm2 of which 0.5 mm2 is occupied by the CDC. In frequency range from DC to 2 kHz, the resolution of the CDC is thermal noise limited, whereas the quantization noise is shaped to higher frequency. After applying a low-pass digital filter with a bandwidth of 1 kHz, the dynamic range is better than 15 bits, corresponding to 3 nm displacement resolution. ...
This thesis presents a capacitive sensing technique which is suitable for measuring small displacements with one floating target electrode. A capacitive sensor interface, which does not require electrical contact with the target, while demonstrating performance comparable with the state-of-the-art, is proposed. The designed prototype is intended for displacement measurement with a measurement range from 10 µm to 100 µm, and a resolution better than 3 nm.
The proposed design implants the sensor capacitor into the input branch of a capacitance-to-digital converter (CDC), which results in a simpler system that saves power and reduces the error sources.
The CDC is taped out in the TSMC 0.18 µm CMOS process with Vdd = 1.8 V. The total chip area is 2.3 mm2 of which 0.5 mm2 is occupied by the CDC. In frequency range from DC to 2 kHz, the resolution of the CDC is thermal noise limited, whereas the quantization noise is shaped to higher frequency. After applying a low-pass digital filter with a bandwidth of 1 kHz, the dynamic range is better than 15 bits, corresponding to 3 nm displacement resolution.
The proposed design implants the sensor capacitor into the input branch of a capacitance-to-digital converter (CDC), which results in a simpler system that saves power and reduces the error sources.
The CDC is taped out in the TSMC 0.18 µm CMOS process with Vdd = 1.8 V. The total chip area is 2.3 mm2 of which 0.5 mm2 is occupied by the CDC. In frequency range from DC to 2 kHz, the resolution of the CDC is thermal noise limited, whereas the quantization noise is shaped to higher frequency. After applying a low-pass digital filter with a bandwidth of 1 kHz, the dynamic range is better than 15 bits, corresponding to 3 nm displacement resolution.