Low-Power Detector Readout ASIC based on Sparse-Event Counting for Scanning-Electron Microscopy

Abstract

This thesis investigates three backend readout architectures for an event counting based scanning electron microscope (SEM) sensor formed by a matrix of detectors. A full adder tree, a critical adder tree, and a novel asynchronous pulse counter design are proposed. The full and critical adder trees are based on a Wallace tree, and provide synchronous summation of the detector outputs, with the critical adder tree reducing power by omitting higher order additions based on expected event rates. The pulse counter introduces a fundamentally different approach by converting asynchronous detector outputs into short pulses that propagate through a modified shift register. By matching latch to latch propagation delays to the pulse width, the design ensures that single pulses shift the register by one position, while overlapping pulses shift it by two. The resulting thermometer code is then synchronously encoded. This architecture eliminates the need for clock distribution to each detector, offering substantial power savings.
All three architectures were implemented and evaluated for a 16 × 16 detector matrix across event rates ranging from 0.01 to 4 total events per 2.5 ns. The full adder tree demonstrated reliable operation across all rates with a power consumption of 62 mW, dominated by clock distribution. The critical adder tree achieved similar reliability with a slightly lower power consumption of 60.5 mW. The pulse counter operated reliably up to 6.0×105 events per second while consuming only 1.26 mW, highlighting the efficiency of asynchronous processing.
A hierarchical, pipelined readout system was developed 128 × 128 detector matrix with a sampling period of 2.5 ns. Clock distribution was implemented using a balanced H tree, resulting in less than 100 ps skew from local device mismatches. The use of double data rate memory reduced the global clock frequency from 400 MHz to 200 MHz, reducing power consumption by 170 mW. A model of electron incidence across the detector matrix guided the selection of readout architectures for the first pipeline stage. Regions with higher expected event rates were implemented using the critical adder tree to minimize error, while lower rate regions used the pulse counter to minimize power. Subsequent pipeline stages were implemented using the critical adder tree.
The final mixed architecture system achieved a total power consumption of 0.9 W with an error rate of 232 ppm, compared to 4.3 W and zero errors for an implementation using only the critical adder tree. These results demonstrate a substantial and tunable trade off between power consumption and accuracy, validating the feasibility of low power, high rate readout for next generation SEM detector arrays.