This study introduces a methodology for forecasting accelerator performance in Particle Physics algorithms. Accelerating applications can require significant engineering effort, prototyping and measuring the speedup that might finally result in disappointing accelerator performance. The proposed methodology involves performance modelling and forecasting, enabling the prediction of potential speedup, identification of promising acceleration candidates, prior to any significant programming investment. By predicting worst-case scenarios, the methodology assists developers in deciding whether an application can benefit from acceleration, thus optimising effort. A Monte Carlo simulation example demonstrates the effectiveness of the proposed methodology. The result shows that the methodology provides a reasonable estimate for GPUs and, in the context of FPGAs, the predictions are extremely accurate, within 2% of the realised execution time.

Accurate and secure classifying informal documents related to mental disorders is challenging due to factors such as informal language, noisy data, cultural differences, personal information and mixed emotions. Conventional deep learning models often struggle to capture patterns in informal text, as they miss long-range dependencies, explain words and phrases literally, and have difficulty processing non-standard inputs like emojis. To address these limitations, we expand data dimensionality, transforming and fusing textual data and signs from a 1D to a 2D space. This enables the use of pre-trained 2D CNN models, such as AlexNet, Restnet-50, and VGG-16 removing the need to design and train new models from scratch. We apply this approach to a dataset of social media posts to classify informal documents as either related to suicide or non-suicide content. Our results demonstrate high classification accuracy, exceeding 99%. In addition, our 2D visual data representation conceals individual private information and helps explainability.

Image Aesthetic Quality Assessment (IAQA) spans applications such as the fashion industry, AI-generated content, product design, and e-commerce. Recent deep learning advancements have been employed to evaluate image aesthetic quality. A few surveys have been conducted on IAQA models; however, details of recent deep learning models and challenges have not been fully mentioned. This article aims to fill these gaps by providing a review of deep learning IAQA over the past decade, based on input, process, and output phases. Methodologies for deep learning-based IAQA can be categorized into general and task-specific approaches, depending on the type and diversity of input images. The processing phase involves considerations related to network architecture, learning structures, and feature extraction methods. The output phase generates results such as scoring, distribution, attributes, and description. Despite achieving a maximum accuracy of 91.5%, further improvements in deep learning models are still required. Our study highlights several challenges, including adapting models for task-specific methodology, accounting for environmental factors influencing aesthetics, the lack of substantial datasets with appropriate labels, imbalanced data, preserving image aspect ratio and integrity in network architecture design, and the need for explainable AI to understand the causative factors behind aesthetic judgments.

Full-System (FS) simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Nevertheless, they require careful fine-tuning against real hardware to obtain reliable performance statistics, which can become tedious, error-prone, and time-consuming with typical trial-and-error approaches. We propose a novel, streamlined, component-level calibration methodology to address these shortcomings to validate FS simulation models. Our methodology greatly accelerates the validation process without sacrificing accuracy. It is Instruction Set Architecture (ISA)-agnostic, and can tackle hardware specifications at different levels of detail. We demonstrate its effectiveness by validating FS models against both open-hardware and IP-protected (closed hardware) RISC-V silicon, achieving a mean error of 19%-23% for the SPEC CPU2017 suite in the two cases. We introduce the first open-source RISC-V-based FS-validated simulation models with a complete and replicable methodology.

Processing graphs on a large scale presents a range of difficulties, including irregular memory access patterns, device memory limitations, and the need for effective partitioning in distributed systems, all of which can lead to performance problems on traditional architectures such as CPUs and GPUs. To address these challenges, recent research emphasizes the use of Field-Programmable Gate Arrays (FPGAs) within distributed frameworks, harnessing the power of FPGAs in a distributed environment for accelerated graph processing. This paper examines the effectiveness of a multi-FPGA distributed architecture in combination with a partitioning system to improve data locality and reduce inter-partition communication. Utilizing Hadoop at a higher level, the framework maps the graph to the hardware, efficiently distributing pre-processed data to FPGAs. The FPGA processing engine, integrated into a cluster framework, optimizes data transfers, using offline partitioning for large-scale graph distribution. A first evaluation of the framework is based on the popular PageRank algorithm, which assigns a value to each node in a graph based on its importance. In the realm of large-scale graphs, the single FPGA solution outperformed the GPU solution that were restricted by memory capacity and surpassing CPU speedup by 26x compared to 12x. Moreover, when a single FPGA device was limited due to the size of the graph, our performance model showed that a distributed system with multiple FPGAs could increase performance by around 12x. This highlights the effectiveness of our solution for handling large datasets that surpass on-chip memory restrictions.

Pedestrian detection remains a critical problem in various domains, such as computer vision, surveillance, and autonomous driving. In particular, accurate and instant detection of pedestrians in low-light conditions and reduced visibility is of utmost importance for autonomous vehicles to prevent accidents and save lives. This paper aims to comprehensively survey various pedestrian detection approaches, baselines, and datasets that specifically target low-light conditions. The survey discusses the challenges faced in detecting pedestrians at night and explores state-of-the-art methodologies proposed in recent years to address this issue. These methodologies encompass a diverse range, including deep learning-based, feature-based, and hybrid approaches, which have shown promising results in enhancing pedestrian detection performance under challenging lighting conditions. Furthermore, the paper highlights current research directions in the field and identifies potential solutions that merit further investigation by researchers. By thoroughly examining pedestrian detection techniques in low-light conditions, this survey seeks to contribute to the advancement of safer and more reliable autonomous driving systems and other applications related to pedestrian safety. Accordingly, most of the current approaches in the field use deep learning-based image fusion methodologies (i.e., early, halfway, and late fusion) for accurate and reliable pedestrian detection. Moreover, the majority of the works in the field (approximately 48%) have been evaluated on the KAIST dataset, while the real-world video feeds recorded by authors have been used in less than 6 % of the works.

Collision recovery is considered one of the main potentials for improving bulk reading speed in the UHF radio identification (RFID) system. The collision occurs when two or more tags reply at the same time. State-of-the-art collision recovery algorithms rely on perfect channel state information (CSI), which is unrealistic. Moreover, these algorithms neglect the rate tolerance, that is, the uncertainty in the bit rate of the tag responses. This paper presents a novel algorithm to estimate all tag parameters, such as tag data rate, number of tags per slot, and CSI, using the Matrix Pencil Method (MPM). The proposed system is compatible with the existing EPCglobal Class-1 Gen-2 RFID standard. The accuracy of the proposed algorithm is evaluated with the different encoding schemes of the tag. The estimated parameters are forwarded to MIMO linear receivers to recover the colliding slots to speed up the identification process. The performance of the three linear receivers; Zero Forcing (ZF), Minimum Mean Square Error (MMSE), and Maximum Likelihood (ML) receivers, is evaluated when the CSI is estimated using the proposed algorithm. All receivers perform similarly due to their different sensitivity to the CSI estimation error. The proposed collision recovery system reduces the time for reading a bulk by at least 13% compared to the literature.

Memristor technology has shown great promise for energy-efficient computing [1] , though it is still facing many challenges [1 , 2]. For instance, the required additional costly electroforming to establish conductive pathways is seen as a significant drawback as it contributes to power and area overheads, and limited device endurance. In this work, we propose a novel forming-free HfO₂ -based ReRAM device with low operating voltages , multi-level capability , and less sensitivity to device-to-device (D2D) and cycle-to-cycle (C2C) variations. The device is fabricated using CMOS-compatible processes, excluding the undesirable complex steps mandatory to manufacture the state-of-the-art forming-free devices [3, 4, 5]. This is accomplished by utilizing the desirable formation energy of Pd-O bonds [6, 7], which creates conducting paths at room temperature while maintaining the analog switching ability of the devices. The proposed ReRAM device holds a great value for dense memories and energy-efficient compute architectures.

Neural Networks (NN) are often trained offline on large datasets and deployed on specialised hardware for inference, with a strict separation between training and inference. However, in many realistic applications the training environment differs from the real world, or data arrives in a streaming fashion and is continuously changing. In these scenarios, the ability to continuously train and update NN models is desirable. Continual learning (CL) algorithms allow training of models on a stream of data. CL algorithms are often designed to work in constrained settings, such as limited memory and computational power, or limitations on the ability to store past data (e.g, due to privacy concerns or memory requirements). High-energy physics experiments are developing intelligent detectors, with algorithms running on computer systems located close to the detector to meet the challenges of increased data rates and occupancies. The use of NN algorithms in this context is limited by changing detector conditions, such as degradation over time or failure of an input signal which might cause the NNs to lose accuracy leading, in the worst case to the loss of interesting events. CL has the potential to solve this issue, using large amounts of continuously streaming data to allow the network to recognise changes, and to learn and adapt to detector conditions. It has the potential to outperform traditional NN training techniques as not all possible scenarios can be predicted and modelled in static training data samples. However, NN training is computationally expensive and when combined with the strict timing requirements of embedded processors deployed close to the detector, current state-of-the-art offline approaches cannot be directly applied to the real-time systems. Alternatives to typical backpropagation-based training that can be deployed on FPGAs for real-time data processing are presented, and their computational and accuracy characteristics are discussed in the context of High-Luminosity LHC.

The Advanced Encryption Standard (AES) is widely recognized as a robust cryptographic algorithm utilized to protect data integrity and confidentiality. When it comes to lightweight implementations of the algorithm, the literature mainly emphasizes area and power optimization, often overlooking considerations related to performance and security. This paper evaluates two of our previously proposed lightweight AES implementations using both profiled and non-profiled attacks. One is an unprotected implementation, and the other one is a protected version using Domain-Oriented Masking (DOM). The findings of this study indicate that the inclusion of DOM in the design enhances its resistance to attacks at the cost of doubling the area.

Applications of Binary Neural Networks (BNNs) are promising for embedded systems with hard constraints on energy and computing power. Contrary to conventional neural networks using floating-point datatypes, BNNs use binarized weights and activations to reduce memory and computation requirements. Memristors, emerging non-volatile memory devices, show great potential as a target implementation platform for BNNs by integrating storage and compute units. However, the efficiency of this hardware highly depends on how the network is mapped and executed on these devices. In this paper, we propose an efficient implementation of XNOR-based BNN to maximize parallelization. In this implementation, costly analog-to-digital converters are replaced with sense amplifiers with custom reference(s) to generate activation values. Besides, a novel mapping is introduced to minimize the overhead of data communication between convolution layers mapped to different memristor crossbars. This comes with extensive analytical and simulation-based analysis to evaluate the implication of different design choices considering the accuracy of the network. The results show that our approach achieves up to 5× energy-saving and 100× improvement in latency compared to baselines.

Modern DRAMs are vulnerable to Rowhammer attacks, demanding robust protection methods to mitigate these attacks. Existing solutions aim at increased resilience by improving design and/or adjusting operation parameters, limit row access count by throttling and prevent bit flips by timely row refreshing. However, scaling these methods for future DRAM technologies may incur significant costs in terms of area, power and/or latency. This study analyses the impact of the values of the neighbouring cells on victim cells and introduces a row alternation protection method, which is a novel approach that alternates the data of attacker rows on each access to lower the chance of bit flips in victim rows. Our analysis show that the minimum Rowhammer count to cause a bitflip in a particular cell does not only depend on vertical neighbours from the attacker row, but also on the value of the horizontal neighbours from the victim row as well as diagonal cells from the attacker row. Row alternation is able to protect the majority of the vulnerable cells (i.e., with 65%) for the DRAM used in our case study and in cases where unsuccessful it significantly increases the average minimum required Rowhammer account by 18%.

Random number generation is key to many applications in a wide variety of disciplines. Depending on the application, the quality of the random numbers from a particular generator can directly impact both computational performance and critically the outcome of the calculation. High-energy physics applications use Monte Carlo simulations and machine learning widely, which both require high-quality random numbers. In recent years, to meet increasing performance requirements, many high-energy physics workloads leverage GPU acceleration. While on a CPU, there exist a wide variety of generators with different performance and quality characteristics, the same cannot be stated for GPU and FPGA accelerators. On GPUs, the most common implementation is provided by cuRAND - an NVIDIA library that is not open source or peer reviewed by the scientific community. The highest-quality generator implemented in cuRAND is a version of the Mersenne Twister. Given the availability of better and faster random number generators, high-energy physics moved away from Mersenne Twister several years ago and nowadays MIXMAX is the standard generator in Geant4 via CLHEP. The MIXMAX original design supports parallel streams with a seeding algorithm that makes it especially suited for GPU and FPGA where extreme parallelism is a key factor. In this study we implement the MIXMAX generator on both architectures and analyze its suitability and applicability for accelerator implementations. We evaluated the results against “Mersenne Twister for a Graphic Processor” (MTGP32) on GPUs which resulted in 5, 13 and 14 times higher throughput when a 240, 17 and 8 sized vector space was used respectively. The MIXMAX generator coded in VHDL and implemented on Xilinx Ultrascale+ FPGAs, requires 50% fewer total Look Up Tables (LUTs) compared to a 32-bit Mersenne Twister (MT-19337), or 75% fewer LUTs per output bit. In summary, the state-of-the art MIXMAX pseudo random number generator has been implemented on GPU and FPGA platforms and the performance benchmarked.

Background and purpose: Physiological motion impacts the dose delivered to tumours and vital organs in external beam radiotherapy and particularly in particle therapy. The excellent soft-tissue demarcation of 4D magnetic resonance imaging (4D-MRI) could inform on intra-fractional motion, but long image reconstruction times hinder its use in online treatment adaptation. Here we employ techniques from high-performance computing to reduce 4D-MRI reconstruction times below two minutes to facilitate their use in MR-guided radiotherapy. Material and methods: Four patients with pancreatic adenocarcinoma were scanned with a radial stack-of-stars gradient echo sequence on a 1.5T MR-Linac. Fast parallelised open-source implementations of the extra-dimensional golden-angle radial sparse parallel algorithm were developed for central processing unit (CPU) and graphics processing unit (GPU) architectures. We assessed the impact of architecture, oversampling and respiratory binning strategy on 4D-MRI reconstruction time and compared images using the structural similarity (SSIM) index against a MATLAB reference implementation. Scaling and bottlenecks for the different architectures were studied using multi-GPU systems. Results: All reconstructed 4D-MRI were identical to the reference implementation (SSIM > 0.99). Images reconstructed with overlapping respiratory bins were sharper at the cost of longer reconstruction times. The CPU + GPU implementation was over 17 times faster than the reference implementation, reconstructing images in 60 ± 1 s and hyper-scaled using multiple GPUs. Conclusion: Respiratory-resolved 4D-MRI reconstruction times can be reduced using high-performance computing methods for online workflows in MR-guided radiotherapy with potential applications in particle therapy.

Data sanitization in the context of Internet of Things (IoT) privacy refers to the process of permanently and irreversibly hiding all sensitive information from vast amounts of streaming data. Taking into account the dynamic and real-time characteristics of streaming IoT data, we propose a parallel evolutionary Privacy-Preserving Data Mining (PPDM), called High-performance Evolutionary Data Sanitization for IoT (HEDS4IoT), and implement two mechanisms on a Graphics Processing Units (GPU)-aided parallelized platform to achieve real-time streaming protected data transmission. The first mechanism, the Parallel Indexing Engine (PIE), generates retrieval index lists from the dataset using GPU blocks. These lists are used in place of the dataset during the PPDM process. The second mechanism, called Parallel Fitness Function Engine (PF2E), parallelizes the index lists on the GPU threads to speed up the computation of the quality of solutions generated by the evolutionary algorithm, in which deferential evolution is adopted as the evolutionary algorithm. In addition to the ability for Big data, the HEDS4IoT can be adaptively adjusted for dynamic nature of IoT where new streaming data is considered for data sanitization. Our experimental results with extensive benchmarks show that, at the kernel level, the PIE and PF2E mechanisms are averagely 33.5x and 53.7x faster than their CPU-implemented version, respectively. At the application level, our findings demonstrate that the HEDS4IoT can perform the PPDM process 47.7x faster than some of the state-of-art methods.

In dense radio frequency identification (RFID) systems, reducing reading times is crucial. For tag anti-collision management, most RFID systems rely on Frame Slotted ALOHA (FSA). The most common method used to reduce the reading time for large tag populations is the optimization of the number of slots per frame. Each slot in real RFID systems has a different duration determined by its type (idle, successful, or colliding). Furthermore, by detecting the strongest transponder, colliding slots can be converted into successful slots, a phenomenon known as the capture effect. The strongest tag reply can also be intentionally detected by enhancing the reader's capabilities with collision recovery. RFID readers may also be capable of identifying slot types using the physical layer and reducing the colliding slot time because in this case, the reader can immediately terminate the connection as there is no reason to reply with an invalid acknowledge and wait for the time-out. This paper presents an exhaustive analysis of the effect of slot type identification and capture probability on the frame length in the presence of different tag cardinality estimation techniques. Additionally, the effect of the new optimized frame length on the total reading time reduction is addressed with different tag encoding schemes. Theoretically, experimental results for FM0 encoding show that our technique achieves a total reading time reduction between 5.5% and 11.3% over methods that do not take into account slot type identification in the frame length optimization. For Miller encoding scheme with $M=2, 4$ , and 8 the reading time is decreased by 9%, 6%, and 1% respectively. The maximum reading time reductions are achieved at collision recovery probabilities values of 0.4 for FM0 and Miller with $M = 2$ and 0.45 & 0.6 for $M = 4$ , and $M = 8$ , respectively. In case the reader does not have any collision recovery capability and the Schoute algorithm is used to estimate the tag cardinality, the maximum reading time reductions dropped to 3.9%, 2.6%, 1.7%, and 1.3% for FM0, Miller encoding scheme with $M=2, 4$ , and 8, respectively. However, if a more optimized tag cardinality estimation technique is used such as the Schoute algorithm, the maximum reading time reductions are 7.8%, 4.8%, 3.3%, and 2.4% for FM0, Miller encoding scheme with $M=2, 4$ and 8, respectively.

One of the main obstacles for low latency bulk reading in UHF RFID systems is collision occurrence. State-of-the-art high-speed identification methods mostly rely on collision recovery techniques or collision avoidance algorithms. Collision recovery can be done by enhancing the physical layer capabilities to support this feature. Usually, the probability of collision occurrence can be reduced by carefully optimizing the frame length and accurately estimating the number of tags in the interrogation area. In this paper, bulk reading time is reduced by detecting collisions in tag replies. More precisely, the RFID reader identifies slot types using the tag replies spectrum and the deviation in tag data rates which is known as rate tolerance. This novel reader feature distinguishes two types of collided slots; identified collided slots with shorter duration as compared to the non-identified ones. Hence, our technique drastically improves RFID tag reading times. Our experimental results show that the proposed technique can reduce bulk reading times by 10% compared to conventional receivers at SNR greater than 20dB.

Application-specific systems with FPGA accelerators are often designed using high-level synthesis or hardware construction tools. Nowadays, there are many frameworks available, both open-source and commercial. In this work, we aim at a fair comparison of several languages (and tools), including Verilog (our baseline), Chisel, Bluespec System Verilog (Bluespec Compiler), DSLX (XLS), MaxJ (MaxCompiler), and C (Bambu and Vivado HLS). Our analysis has been carried out using a representative example of 8×8 inverse discrete cosine transform (IDCT), a widely used algorithm engaged in JPEG and MPEG decoders. The metrics under consideration include: (a) the degree of automation (how much less code is required compared to Verilog), (b) the controllability (possibility to achieve given design characteristics, namely a given ratio of the performance and area), and (c) the flexibility (ease of design modifications to achieve certain characteristics). Rather than focusing on computational kernels only, we use AXI-Stream wrappers for the synthesized implementations, which allows adequately evaluating characteristics of the designs when they are used as parts of real systems. Our study shows clear examples of what impact specific optimizations (tool settings and source code modifications) have on the overall system performance and area. It emphasizes how important is to be able to control the balance between the communication interface utilization and the computational kernel performance and delivers clear guidelines for the next generation tools for designing FPGA-accelerator-based systems.

Performing analysis on large graph datasets in an energy-efficient manner has posed a significant challenge; not only due to excessive data movements and poor locality, but also due to the non-optimal use of high sparsity of such datasets. The latter leads to a waste of resources as the computation is also performed on zero's operands which do not contribute to the final result. This paper designs a novel graph processing accelerator, SparseMEM, targeting sparse datasets by leveraging the computing-in-memory (CIM) concept; CIM is a promising solution to alleviate the overhead of data movement and the inherent poor locality of graph processing. The proposed solution stores the graph information in a compressed hierarchical format inside the memory and adjusts the workflow based on this new mapping. This vastly improves resource utilization, leading to higher energy and permanence efficiency. The experimental results demonstrate that SparseMEM outperforms a GPU-based platform and two state-of-the-art in-memory accelerators on speedup and energy efficiency by one and three orders of magnitude, respectively.

Smart computing has demonstrated huge potential for various application sectors such as personalized healthcare and smart robotics. Smart computing aims bringing computing close to the source where the data is generated or stored. Memristor-based Computation-In-Memory (CIM) has the potential to realize such smart computing for data and computation intensive applications. This paper presents an overview and design present of CIM, covering from the architecture and circuit level down to the device level. On the circuit and device level, accelerators for machine learning will be presented and discussed, focusing on variability and reliability effects. We will discuss these aspects for Redox-based Resistive Random Access Memories (ReRAM) based on the Valence Change Mechanism (VCM) by employing the compact model JART VCM v1b.