Addressing non-idealities in Resistive Random Access Memories (RRAMs) is crucial for their successful commercialization. For example, the inherent resistance drift that occurs during consecutive read operations can induce Read Disturb Faults (RDF), leading to functional errors. This paper analyzes and characterizes the resistance drift and the RDF based on data measurements and presents a physics-based RRAM compact model that incorporates these non-idealities. Additionally, an in-field mitigation scheme is proposed, leveraging bidirectional read operations to balance the resistance. The scheme is implemented and validated through circuit simulations, both for RRAM used as memory and for RRAM-based computation-in-memory microarchitectures for deep neural networks. The results demonstrate that RRAM without any mitigation scheme can start failing after 8,000 consecutive reads, while our mitigation scheme ensures that the memory remains functional even after 10⁶ consecutive reads. Furthermore, the results indicate that using the MNIST dataset as a case study, the accuracy can drop significantly from 86% to as low as 12.5% without any mitigation scheme. In contrast, the proposed mitigation scheme improves this accuracy up to 84.2%.

Introduction: In 2012, potassium and sodium ion channels in Hodgkin-Huxley-based brain models were shown to exhibit memristive behavior. This positioned memristors as strong candidates for implementing biologically accurate artificial neurons. Memristor-based brain simulations offer advantages in energy efficiency, scalability, and compactness, benefiting fields such as soft robotics, embedded systems, and neuroprosthetics. Methods: Previous approaches used current-controlled Mott memristors, which poorly matched the voltage-controlled nature of ion channels. This study employs volatile, oxide-based memristors that leverage electric-field-driven oxygen-vacancy migration to emulate voltage-dependent channel behavior. We selected candidate WOx and NbOx memristors and modeled their dynamics to verify performance as Hodgkin-Huxley potassium channels. Results: The device exhibits sigmoidal gating and voltage-dependent time constants consistent with the theoretical model. By scaling the passive circuitry around the memristors, we show that they capture the essential mechanisms of potassium ion-channels, although spike height is reduced due to strong non-linear voltage-dependence. Still, by cascading multiple compartments, typical spike propagation is retained. Discussion: This is the first demonstration of a voltage-controlled memristor replicating the Hodgkin-Huxley potassium channel, validating its potential for more efficient brain simulation hardware.

From the first spark of inspiration to the final forward-looking horizon, this thesis unfolds as a journey to re-imagine the foundations of computation. We merge breakthroughs in materials science, electronic device engineering, and deep generative learning to confront three of modern computing grandest challenges: the energy inefficiencies of classical architectures, the scaling limitations of neuromorphic hardware, and the exponential complexity of quantum systems.

We begin by identifying a threefold bottleneck at the heart of contemporary information processing. On one hand, the von Neumann architecture separates memory from logic, incurring high energy and latency costs. On another, quantum systems, with their exponentially expanding state spaces, defy conventional methods of characterization and control. Bridging these extremes demands both new materials and new paradigms: architectures that think and learn within memory itself and operate seamlessly across room-temperature and cryogenic domains. Our mission is to forge a unified computing framework that fuses neuromorphic principles, cryogenic and room-temperature memristors, and machine intelligence with quantum state tomography (QST).

The conceptual groundwork follows. Inspired by biological neurons, we explore how computation and memory can coexist within memristive architectures. Memristors, particularly resistive switching devices such as HfO2-based ReRAM, emulate synaptic plasticity, enabling analog tuning and in-memory processing. We investigate both spiking and non-spiking neural models, contextualizing their use in QST. The core idea of computation-in-memory (CiM) emerges, performing neural operations directly within dense memristor crossbars, bypassing the von Neumann bottleneck. This unifying concept becomes the architectural backbone of our hybrid classical–quantum platform.

Our theoretical framework spans silicon physics, memristive mechanisms, and the formalism of quantum state reconstruction. We dissect electron-beam-induced processing (EBIP) as a route to room-temperature silicon device fabrication. We examine the physics of OxReRAM switching, ion migration, interfacial engineering, and energy barriers, and we extend this understanding to cryogenic regimes. In parallel, we articulate the formal structure of QST, density matrices, POVMs, and data scaling as 4^N for N qubits, where neural networks emerge as natural generative or inference engines. Variational autoencoders, especially spiking VAEs (SVAEs), form the probabilistic bridge between neuromorphic learning and quantum reconstruction. The materials narrative begins with innovation in silicon processing. Abandoning high-temperature furnaces, we deploy spin-coated liquid polysilanes and transform them into functional amorphous silicon films via focused EBIP. STEM–EELS imaging, residual-gas analysis, and electrical characterization confirm uniform, low-defect films exhibiting stable ohmic behavior over months. This approach enables nanoscale precision and compatibility with flexible substrates, key for next-generation neuromorphic hardware.

ReRAM devices, long hampered by high-voltage electroforming and poor uniformity, are re-engineered. By designing Pd/HfO2 interfaces, we realize forming-free OxReRAM cells that switch at sub-2V, support multibit states, and retain data over 10^4 s. Atomic-scale analysis reveals a Pd–O–Hf interfacial layer that stabilizes low-bias conductive pathways. These devices achieve endurance and energy consumption in the picojoule range, validating them as efficient synaptic elements for in-memory computing. At cryogenic temperatures, the same memristive principles enable a new frontier: Cryo-Memristors for spin-qubit control. Operating reliably at 4 K, Pt/Ti/HfO2-based memristors and their modified variants (M-PtHT) serve as low-noise, multi-bit programmable gain elements for scalable quantum control electronics. Embedded near the quantum layer, these devices synthesize analog bias voltages with sub-100\,µV resolution, drastically reducing the wiring complexity, heat load, and latency in large-scale qubit arrays. Statistical analysis shows linear resistance variation and stable multi-bit retention even at 4\,K, confirming their potential as cryogenic analog memory elements for autonomous qubit tuning and adaptive quantum feedback. This chapter bridges device physics and quantum hardware, demonstrating that memristive programmability can extend beyond neuromorphic computing into the quantum domain.

We confront QST through the lens of machine learning. A diverse suite of neural architectures, FCN, CNN, RNN, RBM, CGAN, and Transformer, is deployed to reconstruct quantum states from simulated measurement data. Among them, CNNs deliver the best trade-off between fidelity and computational time, especially under expectation-based measurements. Yet, the SVAE architecture marks a turning point: as a generative probabilistic model, it achieves high-fidelity reconstructions even under sparse and noisy data, generalizing to higher qubit counts (up to 8) and scaling sub-exponentially in runtime. Its latent-space encoding of high-dimensional quantum information renders it ideal for real-time, energy-efficient inference when implemented on memristive crossbars. Simulations incorporating real device characteristics confirm that our forming-free and cryogenic OxReRAM-based CiM arrays can physically sustain deep QST networks. Memristor crossbars perform rapid in-memory matrix–vector multiplications, reducing inference energy by orders of magnitude compared to digital processors. Together, these results establish a scalable, hardware-aware path toward hybrid classical–neuromorphic–quantum computing.

We conclude by reflecting on the broader implications. This work demonstrates that room-temperature EBIP enables sustainable silicon fabrication; that forming-free OxReRAM devices can be engineered for reliable analog switching; that Cryo-Memristors enable scalable, low-power qubit control; and that generative neural networks, especially SVAEs, offer a pathway to efficient, hardware-embedded quantum state reconstruction. Looking ahead, these innovations converge toward cryogenic integration with quantum processors, adaptive quantum feedback via spiking neuromorphic circuits, and the eventual realization of intelligent, energy-aware quantum systems.

Through every chapter, one theme resounds: the dissolution of boundaries, between memory and logic, between classical and quantum, between matter and model. This thesis lays the foundation for a new kind of computing, one that learns like the brain, reasons like a physicist, and computes like the future demands.

Trust is important in public health communication to culturally and linguistically diverse (CALD) communities during pandemics. This empirical research, using quantitative data from 107 foreign nationals at a university in Shanghai, probes into how trust varied in official translation services (OTS) and non-official translation services (NOTS) during COVID-19. Statistical analysis was carried out by IBM SPSS Statistics 26 and it was found that (1) NOTS which are more frequently used are more trusted compared with OTS; (2) NOTS are uncorrelated with demographics while OTS are correlated with demographics, among which education and trust in OTS suggest a linear positive relationship (Sig. = 0.003, β = 0.467), whereas age and trust in OTS suggest a linear negative relationship (Sig. = 0.027, β = −0.348); (3) there is a positive relationship between the frequency of using services and trust, i.e., higher frequency implies higher trust. The findings of this case study can have implications for policy makers and the representatives of CALD communities.

Resistive Random Access Memories (RRAMs) are now undergoing commercialization, with substantial investment from many semiconductor companies. However, due to the immature manufacturing process, RRAMs are prone to exhibit new failure mechanisms and faults, which should be efficiently detected for high-volume production. Some of those faults are hard-to-detect, and require specific Design-for-Testability (DfT) circuit design. This paper proposes a DfT based on a parallel-reference write circuit that can detect all single-cell RRAM array faults: strong faults (directly causing logic errors) as well as weak faults (caused by parametric deviations). The scheme replaces the regular write driver, and enables the monitoring and comparison of the write current against multiple references during a single write operation. Hence, it serves as a DfT scheme and as a normal write circuit simultaneously. In addition, it enhances production testing speed and online fault detection, while keeping the area overhead low. Furthermore, the DfT is configurable for efficient diagnosis and yield learning. The results of the simulations performed do not only show that the DfT can detect single-cell conventional faults (due to interconnects and contacts) as well as unique RRAM faults (based on silicon data) that have been demonstrated to exist, but also that the DfT is robust to process variations.

Memristor technology has shown great promise for energy-efficient computing [1] , though it is still facing many challenges [1 , 2]. For instance, the required additional costly electroforming to establish conductive pathways is seen as a significant drawback as it contributes to power and area overheads, and limited device endurance. In this work, we propose a novel forming-free HfO₂ -based ReRAM device with low operating voltages , multi-level capability , and less sensitivity to device-to-device (D2D) and cycle-to-cycle (C2C) variations. The device is fabricated using CMOS-compatible processes, excluding the undesirable complex steps mandatory to manufacture the state-of-the-art forming-free devices [3, 4, 5]. This is accomplished by utilizing the desirable formation energy of Pd-O bonds [6, 7], which creates conducting paths at room temperature while maintaining the analog switching ability of the devices. The proposed ReRAM device holds a great value for dense memories and energy-efficient compute architectures.