Addressing non-idealities in Resistive Random Access Memories (RRAMs) is crucial for their successful commercialization. For example, the inherent resistance drift that occurs during consecutive read operations can induce Read Disturb Faults (RDF), leading to functional errors. This paper analyzes and characterizes the resistance drift and the RDF based on data measurements and presents a physics-based RRAM compact model that incorporates these non-idealities. Additionally, an in-field mitigation scheme is proposed, leveraging bidirectional read operations to balance the resistance. The scheme is implemented and validated through circuit simulations, both for RRAM used as memory and for RRAM-based computation-in-memory microarchitectures for deep neural networks. The results demonstrate that RRAM without any mitigation scheme can start failing after 8,000 consecutive reads, while our mitigation scheme ensures that the memory remains functional even after 10⁶ consecutive reads. Furthermore, the results indicate that using the MNIST dataset as a case study, the accuracy can drop significantly from 86% to as low as 12.5% without any mitigation scheme. In contrast, the proposed mitigation scheme improves this accuracy up to 84.2%.

The development of Ferroelectric Field-Effect Transistor (FeFET) manufacturing requires high-quality test solutions, yet research on FeFET testing is still in a nascent stage. To generate a dedicated test method for FeFETs, it is critical to have a deep understanding of manufacturing defects and accurately model them. In this work, we introduce the unique defect, Anomalous Charge Trapping (ACT), in FeFETs. The ACT-defective FeFET is characterized, and the physical mechanism of the defect is explained. Then, we apply the Deviceaware Test (DAT) method to design a specific ACT-defective FeFET model, which includes the physical impact of the defect on the electrical parameters of defect-free models, and calibrate the model with measurement data. Fault modeling is performed based on circuit-level simulations, and dedicated test solutions are proposed.

While Resistive RRAM (RRAM) provides appealing features for artificial neural networks (NN) such as low power operation and high density, its conductance variation can pose significant challenges for synaptic weight storage. This paper reports an experimental evaluation of the conductance variations of manufactured RRAMs memory cells at the memory array level. Variability is evaluated with respect to the RRAM low resistance state (LRS) and high resistance state (HRS) conductance ratio. This ratio is selected as the parameter of interest as it guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell is in storing and retrieving data. The measurement results show that conductance ratio is significantly influenced by variability. Using these findings, the performance of an artificial neural network that uses individual RRAM cells for synaptic weight storage is evaluated in relation to conductance variability. It is shown that RRAM variability can heavily affect the network behavior, resulting in a substantial decrease in the classification accuracy during inference.

Edge AI accelerators have revolutionized intelligent information processing, enabling applications, such as self-driving cars and low-power IoT devices. Design efforts prioritize computational power and energy efficiency. Nevertheless, testability is also critical for in-field, reliable operation, especially for novel architectures such as memristive, analog Computation-in-Memory (CIM) cores. These structures combine emerging Resistive Random Access Memory (RRAM) with CMOS peripherals to efficiently implement vector-matrix-multiplication (VMM) operations for inference. Current research on AI Accelerator testing relies on functional test patterns, derived from abstract and unrealistic fault models. This paper presents a novel structural testing methodology for CIM VMM circuits. The methodology utilizes device-level defect models and defines new fault models for CIM VMM. The resulting test patterns are optimized to maximize defect coverage and minimize test time, since they require only a single write operation per victim cell.

This dissertation, conducted within the discipline of Electronic Science and Technology (specialization in Microelectronics and Solid-State Electronics), focuses on Resistive Random Access Memory (RRAM), an emerging non-volatile memory technology known for its high density and zero static power consumption. RRAM enables fast write and read operations in the nanosecond range and supports Computation-in-Memory (CIM), making it a strong candidate to replace Flash or even Dynamic Random Access Memory (DRAM). Recognizing its potential, both academic institutions and industry leaders have been actively developing RRAM prototypes, with some already reaching the commercial market. To ensure reliability, high-quality testing is essential for guaranteeing product quality.

This dissertation mainly focuses on developing effective test methodologies and robust designs for RRAMs. We begin by examining the RRAM manufacturing process and identifying potential physical defects at each stage through a comprehensive literature review and silicon measurements. To facilitate in-depth analysis, we develop a complete and systematic RRAM simulation platform, integrating a MATLAB-based simulation controller and fault analysis scripts integrated with a complete RRAM circuit design. The controller automates and manages all simulation procedures, while the circuit design comprises a 1T-1R memory array along with essential peripheral components such as write drivers and sense amplifiers. To achieve fast and accurate electrical simulations, we introduce two compact models for RRAMs. These models are optimized and calibrated using extensive measurement data from RRAM devices. We further calibrate the model with industrial measurements from ST Microelectronics. It enables robust device/circuit co-design, accounting for PVT variations and ensuring the reliability and efficiency of RRAM systems.....

Resistive Random Access Memories (RRAMs) are now undergoing commercialization, with substantial investment from many semiconductor companies. However, due to the immature manufacturing process, RRAMs are prone to exhibit new failure mechanisms and faults, which should be efficiently detected for high-volume production. Some of those faults are hard-to-detect, and require specific Design-for-Testability (DfT) circuit design. This paper proposes a DfT based on a parallel-reference write circuit that can detect all single-cell RRAM array faults: strong faults (directly causing logic errors) as well as weak faults (caused by parametric deviations). The scheme replaces the regular write driver, and enables the monitoring and comparison of the write current against multiple references during a single write operation. Hence, it serves as a DfT scheme and as a normal write circuit simultaneously. In addition, it enhances production testing speed and online fault detection, while keeping the area overhead low. Furthermore, the DfT is configurable for efficient diagnosis and yield learning. The results of the simulations performed do not only show that the DfT can detect single-cell conventional faults (due to interconnects and contacts) as well as unique RRAM faults (based on silicon data) that have been demonstrated to exist, but also that the DfT is robust to process variations.

The Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is on its way to commercialization. However, the development of high-quality test solutions for STT-MRAMs poses challenges due to the specific working mechanism of the core element of the STT-MRAM bit cells, i.e., the magnetic tunnel junction (MTJ), which involves both a magnetic field and spin-transfer torque. This property can introduce defects unique to MTJs which may escape from test programs that consist solely of functional write and read operations, like march tests. Hence, it is important to develop test solutions that go beyond conventional march tests. This paper explores the effect of applying an external magnetic field (H_ext) on the test quality and test time of STT-MRAMs, which could be achieved by integrating one or more magnets in the Automated Test Equipment (ATE) setup. A framework for these so-called H_ext-assisted tests is presented and implemented for all known conventional and unique defects. The paper demonstrates that the H_ext-assisted tests offer superior coverage and/or lower test time compared to regular functional tests, like march tests. The effectiveness of these tests are validated through silicon measurements.

While Resistive RRAM (RRAM) offers attractive features for artificial neural networks (NN) such as low power operation and high-density, its conductance variation can pose significant challenges when the storage of synaptic weights is concerned. This paper reports an experimental evaluation of the conductance variations of manufactured RRAMs at the memory array level. Working at the memory array level allows to catch cycle-to-cycle (C2C) as well as device-to-device (D2D) variability and, hence, to propose a realistic evaluation of the conductance variation. Variability is evaluated with respect to the RRAM low resistance state (LRS) and high resistance state (HRS) conductance ratio. This ratio is selected as the parameter of interest as it guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell is in storing and retrieving data. The measurement results show that the conductance ratio is heavily affected by variability. Large spatial and temporal variations are reported, making challenging RRAM-based analog weight storage.

Guaranteeing high-quality test solutions for Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a must to speed up its high-volume production. A high test quality requires maximizing the fault coverage. Detecting permanent faults is relatively simple compared to intermittent faults; the latter are faults (caused by non-environmental conditions) that appear and disappear as a function of time, and are therefore hard to detect. Testing for such faults in STT-MRAMs is even worse considering the Magnetic Tunneling Junction inherent property ‘intrinsic switching stochasticity’, which results in inevitable random write errors. This paper presents a novel Design-for-Testability (DFT) scheme for detecting intermittent faults in STT-MRAMs; it is based on monitoring the write current. The strength of the write current is inversely correlated to the write error rate; when the write current is smaller than the specification, the device is considered faulty. A reduction in the write current can be caused by any defect in the write path of the memory (e.g., interconnects and contacts). Simulation results based on industrial design show that applying DFT yields a superior coverage of intermittent faults compared to functional test methods, such as march tests.

As emerging non-volatile memory (NVM) devices, Ferroelectric Field-Effect Transistors (FeFETs) present distinctive opportunities for the design of ultra-dense and low-leakage memory systems. For matured FeFET manufacturing, it is extremely important to have an understanding of manufacturing defects and accurately model them to develop effective test solutions. This paper introduces a comprehensive framework for defect and fault modeling, which enables the development of test solutions. First, a classification of FeFET manufacturing defects is provided; both conventional defects (such as contacts and interconnect defects) as well as unique FeFET defects are discussed. The latter FeFET specific defect leads to unique faults that cannot be adequately described using traditional modeling approaches. Then, the Device-Aware Test (DAT) method is used to effectively and appropriately model, analyze and develop test solutions for such unique defects; the approach will be illustrated for Stuck-at-Polarization (SAP) defects.

Resistive Random Access Memories (RRAMs) are now undergoing commercialization, with substantial investment from many semiconductor companies. However, due to the immature manufacturing process, RRAMs are prone to exhibit unique defects, which should be efficiently identified for high-volume production. Hence, obtaining diagnostic solutions for RRAMs is necessary to facilitate yield learning, and improve RRAM quality. Recently, the Device-Aware Test (DAT) approach has been proposed as an effective method to detect unique defects in RRAMs. However, the DAT focuses more on developing defect models to aid production testing but does not focus on the distinctive features of defects to diagnose different defects. This paper proposes a Device-Aware Diagnosis method; it is based on the DAT approach, which is extended for diagnosis. The method aims to efficiently distinguish unique defects and conventional defects based on their features. To achieve this, we first define distinctive features of each defect based on physical analysis and characterizations. Then, we develop efficient diagnosis algorithms to extract electrical features and fault signatures for them. The simulation results show the effectiveness of the developed method to reliably diagnose all targeted defects.

Due to the immature manufacturing process, Resistive Random Access Memories (RRAMs) are prone to exhibit new failure mechanisms and faults, which should be efficiently detected for high-volume production. Those unique faults are hard to detect but require specific Design-for-Test (DfT) circuit design. This paper proposes a DfT based on a parallel-reference write circuit that can detect all RRAM array faults during diagnosis, production testing, and its application in the field.

Resistive Random Access Memories (RRAMs) are being commercialized with significant investment from several semiconductor companies. In order to provide efficient and high-quality test solutions to push high-volume production, a comprehensive understanding of manufacturing defects is significantly required. This paper identifies and characterizes the over-RESET phenomenon based on silicon measurements. In our case study, 30% cycles suffered from intermittent extremely high resistance state exceeding the high resistance state criteria. The paper shows the limitations of conventional defect modeling based on linear resistors. To address this challenge, the Device-Aware (DA) defect modeling method is applied; a model of the defective RRAM device is developed and calibrated using measurements to accurately describe the impact of the defect on the electrical behavior of the memory device. Afterward, fault analysis is performed based on the DA defect model, and appropriate fault models are introduced; they show that the DA defect model will sensitize deep (extremely high resistance) state faults. Finally, dedicated test solutions for over-RESET devices are proposed.

Many companies are heavily investing in the commercialization of Resistive Random Access Memories (RRAMs). This calls for a comprehensive understanding of manufacturing defects to develop efficient and high-quality test and diagnosis solutions to push high-volume production. This paper identifies and characterizes a new defect based on silicon measurements; the defect is called Ion Depletion (ID). In our case study, 45% cycles suffered from an intermittent reduction in high resistance state and did not impact low resistance state. The paper shows that the traditional fault modeling based on linear resistors as a defect model is not accurate. To address this challenge, the Device-Aware (DA) defect modeling method is applied; an RRAM model of the defective device is developed and calibrated using measurements to accurately describe the impact of the defect on the electrical behavior of the memory device. Afterward, fault analysis is performed based on the DA defect model, and appropriate fault models are introduced; they show that the ID defect may sensitize undefined state faults. Finally, dedicated test and diagnosis solutions for the ID defect are proposed.

Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This paper analyzes interconnect and contact defects in RRAMs, while considering the impact of the memory Data Background (DB), and proposes test solutions. The complete interconnect and contact defect space in a layout-independent RRAM design is defined. Exhaustive defect injection and circuit simulation are performed in a systematic manner to derive appropriate fault models, not only for single-cell and two-cell coupling faults, but also for multi-cell coupling faults where the DBs are important. The results show the existence of unique 3-cell and 4-cell coupling faults due to e.g., the sneak path in the array induced by defects. These unique faults cannot be detected with traditional RRAM test solutions. Therefore, the paper introduces a test generation method that takes into account the DB, which is able to efficiently detect all these faults; hence, further improving the fault/defect coverage in RRAMs.

The development of Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) mass production requires high-quality test solutions. Accurate and appropriate fault modeling is crucial for the realization of such solutions. This paper targets fault modeling and test generation for all interconnect and contact defects in STT-MRAMs and shows that using the defect injection and circuit simulation for fault modeling without incorporating the impact of magnetic coupling will result in an incomplete set of fault models; hence, not obtaining accurate fault models. Magnetic coupling introduced by the stray field is an inherent property of STT-MRAMs and may foster the occurrence of additional memory faults. Not considering the magnetic coupling clearly will give rise to test escapes. The paper introduces a compact model for STT-MRAM that incorporates the intra- and inter-cell stray field, uses this model to derive the full set of fault models for interconnect and contact defects, and finally proposes an efficient test solution.

The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its fault models and test solutions. The BH defect causes MTJ state to oscillate during write operations, leading to write failures. The characterization of the defect is carried out based on manufactured MTJ devices. Due to the observed non-linear characteristics, the BH defect cannot be modelled with a linear resistance. Hence, device-aware defect modeling is applied by considering the intrinsic physical mechanisms; the model is then calibrated based on measurement data. Thereafter, the fault modeling and analysis is performed based on circuit-level simulations; new fault primitives/models are derived. These accurately describe the way the STT-MRAM behaves in the presence of BH defect. Finally, dedicated march test and a Design-for-Test solutions are proposed.