Defects, Fault Modeling, and Test Development Framework for FeFETs
Changhao Wang (Chinese Academy of Sciences, Politecnico di Torino)
Sicong Yuan (TU Delft - Computer Engineering)
Hanzhi Xun (TU Delft - Computer Engineering)
Chaobo Li (Chinese Academy of Sciences)
Mottaqiallah Taouil (TU Delft - Computer Engineering)
Moritz Fieback (TU Delft - Computer Engineering)
Danyang Chen (Shanghai Jiao Tong University)
Xiuyan Li (Shanghai Jiao Tong University)
Lin Wang (TU Delft - QN/Akhmerov Group, Shanghai Jiao Tong University)
Riccardo Cantoro (Politecnico di Torino)
Chujun Yin (Chinese Academy of Sciences)
Said Hamdioui (TU Delft - Computer Engineering)
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Abstract
As emerging non-volatile memory (NVM) devices, Ferroelectric Field-Effect Transistors (FeFETs) present distinctive opportunities for the design of ultra-dense and low-leakage memory systems. For matured FeFET manufacturing, it is extremely important to have an understanding of manufacturing defects and accurately model them to develop effective test solutions. This paper introduces a comprehensive framework for defect and fault modeling, which enables the development of test solutions. First, a classification of FeFET manufacturing defects is provided; both conventional defects (such as contacts and interconnect defects) as well as unique FeFET defects are discussed. The latter FeFET specific defect leads to unique faults that cannot be adequately described using traditional modeling approaches. Then, the Device-Aware Test (DAT) method is used to effectively and appropriately model, analyze and develop test solutions for such unique defects; the approach will be illustrated for Stuck-at-Polarization (SAP) defects.