Memristors are an emerging technology that enables artificial intelligence (AI) accelerators with high energy efficiency and radiation robustness — properties that are vital for the deployment of AI on-board spacecraft. However, space applications require reliable and precise computations, while memristive devices suffer from non-idealities, such as device variability, conductance drifts, and device faults. Thus, porting neural networks (NNs) to memristive devices often faces the challenge of severe performance degradation. In this work, we show in simulations that memristor-based NNs achieve competitive performance levels on on-board tasks, such as navigation & control and geodesy of asteroids. Through bit-slicing, temporal averaging of NN layers, and periodic activation functions, we improve initial results from around 0.07 to 0.01 and 0.3 to 0.007 for both tasks using RRAM devices, coming close to state-of-the-art levels (0.003−0.005 and 0.003, respectively). Our results demonstrate the potential of memristors for on-board space applications, and we are convinced that future technology and NN improvements will further close the performance gap to fully unlock the benefits of memristors.

Addressing non-idealities in Resistive Random Access Memories (RRAMs) is crucial for their successful commercialization. For example, the inherent resistance drift that occurs during consecutive read operations can induce Read Disturb Faults (RDF), leading to functional errors. This paper analyzes and characterizes the resistance drift and the RDF based on data measurements and presents a physics-based RRAM compact model that incorporates these non-idealities. Additionally, an in-field mitigation scheme is proposed, leveraging bidirectional read operations to balance the resistance. The scheme is implemented and validated through circuit simulations, both for RRAM used as memory and for RRAM-based computation-in-memory microarchitectures for deep neural networks. The results demonstrate that RRAM without any mitigation scheme can start failing after 8,000 consecutive reads, while our mitigation scheme ensures that the memory remains functional even after 10⁶ consecutive reads. Furthermore, the results indicate that using the MNIST dataset as a case study, the accuracy can drop significantly from 86% to as low as 12.5% without any mitigation scheme. In contrast, the proposed mitigation scheme improves this accuracy up to 84.2%.

The goal of the NEUROKIT2E project is to create an open-source Deep Learning framework for edge and embedded AI built around an established European value chain. This framework, called AIDGE, supports a wide range of application areas that operate independently and serve a global user community. It provides easy and fast full-stack solutions from Neural Network design and optimization to AI application development all the way down to hardware implementations while enabling code generation for application-specific targets. This platform provides flexibility for academic users in the AI domain to explore and innovate while allowing them the possibility to prototype systems, ensuring their work aligns well with industrial needs. This paper presents the results and achievements of the first part of this three-year project, along with its roadmap and expected outcomes.

Compute-in-memory (CIM) AI accelerators using non-volatile memories like RRAM enable energy-efficient edge inference by executing Multiply-Accumulate (MAC) operations directly in memory in a single cycle. These designs modify memory cells and analog-to-digital converters (ADCs), introducing faults not seen in standard memories. We present the first structural testing methodology and framework for RRAM-based CIM MAC circuits, including defect and fault models for memory cells and ADCs. Our robust inference-driven tests exercise full MAC functionality, significantly reducing test time compared to traditional methods, and integrating cell and peripheral testing to ensure high reliability, defect coverage, and operational efficiency.

Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) technologies, especially in embedded systems and edge computing. However, due to their physical characteristics, FeFETs exhibit unique defects—such as Threshold Voltage Shifting (TVS) caused by trap charges in the oxide layer—that are not captured by conventional defect models. This study adopts the Device-Aware Test (DAT) methodology to model these defects by incorporating their impact into the electrical parameters, calibrated using measurement data. Defect injection, circuit-level simulations, and fault analysis are performed to derive realistic fault models. Finally, the March algorithm and Design-for-Test (DfT) techniques are proposed to effectively detect these defects.

The test escapes due to latent gate oxide (GOx) shorts have been challenging the relentless pursuit of zero defects, despite of voltage stress testing executed to screen such defects. This scenario underscores a prevailing uncertainty in semiconductor testing, "Are we stressing enough?". Moreover, the increasing complexity of digital circuits, coupled with stringent test time requirements, makes 100% fault coverage an unrealistic targetThis paper presents a solution to optimize voltage stress methodology, and quantify and maximize stress coverage for Integrated Circuits (ICs). The proposed solution involves three key methods. The first method, Critical Thickness Model (CTM), addresses the question "Are we stressing enough?" by determining the minimum stress period of n and p type MOSFET with gate oxide (GOx) thickness in the sub-3nm range. The second method, Stress Coverage Quantification Algorithm (SCQA), assesses actual defect coverage by calculating the percentage of transistors stressed. The third method, Coverage Maximization Algorithm (CMA), aims to reduce customer returns due to GOx shorts by minimizing test escapes. Finally, the paper explores the possibility of Stress Aware ATPG and discusses the trade-offs between under-stressing and over-stressing. The application of CTM resulted in stress time reduction by a factor of 103, thereby reducing test cost and improving yield. Furthermore, SCQA reveals that the ATPG reported coverage is overestimated and differs with SCQA by 6.2%. CMA selected patterns resulted into 2.88% higher coverage, reducing voltage stress test escapes by 10%, improving the quality of voltage stress test.

Olivocerebellar learning is highly adaptable, unfolding over minutes to weeks depending on the task. However, the stabilizing mechanisms of the synaptic dynamics necessary for ongoing learning remain unclear. We constructed a model to examine plasticity dynamics under stochastic input and investigate the impact of inferior olive (IO) reverberations on Purkinje cell (PCs) activity and synaptic plasticity. We explored Upbound and Downbound cerebellar micromodules, which are organized loops of IO neurons, cerebellar nuclei neurons and microzones of PCs characterized by their unique molecular profiles and different levels of baseline firing. Our findings show synaptic weight convergence followed by stability of synaptic weights. In line with their relatively low and high intrinsic firing, we observed that Upbound and Downbound PCs have a propensity for potentiation and depression, respectively, with both PC types reaching stability at differential levels of overall strength of their parallel-fiber (PF) inputs. The oscillations and coupling of IO neurons participating in the Upbound and Downbound modules determine at which frequency band PFs can be stabilized optimally. Our results indicate that specific frequency components drive IO resonance and synchronicity, which, in turn, regulate temporal patterning across Upbound and Downbound zones, orchestrating their plasticity dynamics.

The development of Ferroelectric Field-Effect Transistor (FeFET) manufacturing requires high-quality test solutions, yet research on FeFET testing is still in a nascent stage. To generate a dedicated test method for FeFETs, it is critical to have a deep understanding of manufacturing defects and accurately model them. In this work, we introduce the unique defect, Anomalous Charge Trapping (ACT), in FeFETs. The ACT-defective FeFET is characterized, and the physical mechanism of the defect is explained. Then, we apply the Deviceaware Test (DAT) method to design a specific ACT-defective FeFET model, which includes the physical impact of the defect on the electrical parameters of defect-free models, and calibrate the model with measurement data. Fault modeling is performed based on circuit-level simulations, and dedicated test solutions are proposed.

In recent years, Spin Waves (SWs) have emerged as a promising avenue for beyond-CMOS computing, offering potential advantages in terms of energy efficiency, scalability, and opening avenues towards novel computation paradigms. Until now, SW interference-based gates, for example, the 3 input majority gate (MAJ3), have been proposed and experimentally demonstrated, and an alternative computing paradigm, which relies on SW phase manipulation instead of SW interference has been proposed. However, state-of-the-art SW-based devices suffer from challenges that hinder the realization of larger-scale SW circuits. In this paper, we explore a different computing avenue that relies on Boolean algebra and introduce a SW Switch that makes use of the Voltage Controlled Magnetic Anisotropy (VCMA) effect to allow/block SW propagation. We introduce the device concept, verify its functionality by means of micromagnetic simulations, and perform a circuit-level analysis on EPFL Combinational Benchmarking Suite circuits. As no SW generation and SW read transducers energy consumption experimental data is available we evaluate their upper bound values for which SW implementations can outperform CMOS counterparts. We implement the circuits by means of state-of-the-art SW technologies and the proposed method, compute the upper bound values, and our results indicate that on average the proposal is increasing the upper bound by about 1.2 ×. Subsequently, we consider SW read transducers energy consumption estimates reported in the literature and argue that while they seem appropriate for evaluating SW Boolean switching gates they have to be multiplied with a factor m>1 to capture the extra complexity of generating the output value for SW interference and Phase manipulation SW gates. Our evaluations indicate that the SW Switch-based approach reduces the energy consumption by 1.2504 × 1.4973 × 1.7443 ×, and 1.9912 ×, when compared to the interference approach, and by 1.2478 ×, 1.4947 ×, 1.7416 ×, and 1.9886 ×, when compared to the phase shifting approach, for m=1.25,1.5,1.75,2, respectively. We finally highlight system level advantages of our proposal and conclude that SW Boolean switching gates are opening the most promising avenue towards energy effective SW computing.

Resistive Random-Access Memories (ReRAMs) represent a promising candidate to complement and/or replace CMOS-based memories adopted in several emerging applications. Despite all their advantages – mainly CMOS process compatibility, zero standby power, and high scalability and density – the use of ReRAMs in real applications depends on guaranteeing their quality after manufacturing. As observed in CMOS-based memories, ReRAMs are also susceptible to manufacturing deviations, including defects and process variations, that can cause faulty behaviors different from those observed in CMOS technology, increasing not only the manufacturing test complexity but also the time required to perform the test. In this context, this paper proposes to study the use of temperature to facilitate fault propagation in ReRAMs, reducing the required test time. A case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library was adopted. During the proposed study, a total of 17 defects were injected in different positions of the ReRAM cell, and their respective faulty behavior was classified into conventional and unique faults, considering three different temperatures (25, 100, and -40 °C). The obtained results show that the temperature can, depending on the position of the defect, facilitate fault propagation, which reduces the time required for performing manufacturing testing.

Computational-neuroscience research is increasingly in need of larger, biophysically realistic brain models. These analog-in-nature models build upon the Hodgkin-Huxley (HH) formalism and are run on digital, high-performance computing systems making simulation very computationally expensive. In circuit form, these models are theoretically suitable for efficient analog implementation. However, the ion-channel components –predominantly, sodium and potassium– are nonlinear, time-varying resistors, lacking an efficient implementation. Chua et al. proved that these ion-channel models are in fact memristors –devices with a conductance as a function of applied-voltage history– claiming that “memristors are the right stuff for building brains”. However, the kind of actual memristor implementation that is the right one for building brains is not defined. In this article, the device class and characteristics of such memristors are defined and existing memristive implementations of HH-like designs are then reviewed. Surprisingly, although often misclassified as such, no physical implementation currently exists that replicates the original HH equations faithfully or efficiently. Having put forward the desired memristor properties, a design guide for screening suitable memristor designs is then proposed. Screening the existing literature reveals that suitable devices likely already exist for potassium ion-channel emulation, while none exists for sodium; this calls for further investigation of higher-order, voltage-controlled and volatile memristors.

Structural testing has been very successful in the VLSI manufacturing process to screen out faulty devices and provide high outgoing product quality. However, recent reported data show that existing solutions are not good enough for advanced technology nodes and emerging device technologies. This paper discusses a new manufacturing test approach called DeviceAware Test (DAT), applies it to different flavors of emerging devices, and its potential to be used beyond just manufacturing test.

Approximately one-third of individuals with chronic epilepsy, a condition resulting from uncontrolled brain activity, do not respond to medication. Animal models are widely used to investigate the mechanism underlying epilepsy, so better drug treatments can be developed for this disease. In such studies, epileptiform activity, assessed by EEG recordings, can be used as a marker for the development of the disease. However, the analysis of EEG recordings is typically done manually, which is time-consuming, subject to observer bias, error-prone, and lacks consistency and efficiency. In this paper, we develop a novel automated methodology for detecting and classifying epileptiform activity, which is tested using the intrahippocampal kainic acid (IHKA) mouse model, a representation of human temporal lobe epilepsy. For that, EEG/LFP recordings are obtained from biological experiments using the IHKA mouse model for data acquisition. We use a spike detection method that combines an improved version of the nonlinear energy operator (NEO) with the automatic NEO thresholding (ANT) algorithm. The proposed method is implemented in Python as an automated and time-efficient algorithm, given its adaptability to different spike and epileptiform event criteria, making it suitable for use in preclinical and potentially future clinical studies. Using our proposed methodology, we achieve a 93.1% accuracy in detecting epileptiform events and a 95.8% accuracy in classification. Moreover, the time for analysis of EEG recordings was reduced by 98.8% compared to manual analysis. Additionally, to demonstrate the potential of the algorithm for brain–machine interfaces (BMI) applications, we develop a hardware architecture and implement it using both an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA). The FPGA shows the feasibility of near real-time implementation, and for our ASIC implementation, we achieve a post-layout area of 9114 µm² with a dynamic power consumption of 16.09 μW using TSMC 40 nm technology.

Full-System (FS) simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Nevertheless, they require careful fine-tuning against real hardware to obtain reliable performance statistics, which can become tedious, error-prone, and time-consuming with typical trial-and-error approaches. We propose a novel, streamlined, component-level calibration methodology to address these shortcomings to validate FS simulation models. Our methodology greatly accelerates the validation process without sacrificing accuracy. It is Instruction Set Architecture (ISA)-agnostic, and can tackle hardware specifications at different levels of detail. We demonstrate its effectiveness by validating FS models against both open-hardware and IP-protected (closed hardware) RISC-V silicon, achieving a mean error of 19%-23% for the SPEC CPU2017 suite in the two cases. We introduce the first open-source RISC-V-based FS-validated simulation models with a complete and replicable methodology.

SRAM Physical Unclonable Functions (PUFs) serve as security primitives and can be used to generate random and unique identifiers, which makes their reliability crucial. The reliability is affected by aging and in particular Bias Temperature Instability (BTI), which in turn affects the PUF responses over time typically measured by the Hamming distance (HD). In this work, we model the BTI impact on SRAM PUF reliability for 14 nm FinFET technology and evaluate the reliability of SRAM PUFs using both simulation and silicon measurements. Additionally, we explore the effectiveness of an anti-aging technique on SRAM PUF reliability. Our simulation model and results (which include process variation and circuit noise) are validated with silicon measurements. From them we conclude the following: 1) there exists a direct correlation between BTI and the Hamming distance of an SRAM PUF, where its reliability decreases with 6% over a 6-month period due to aging, and 2) applying anti-aging patterns improves the Hamming distance and hence the reliability with 3% over a 6-month period.

With the rise of energy-constrained smart edge applications, there is a pressing need for energy-efficient computing engines that process generated data locally, at least for small and medium-sized applications. To address this issue, this paper proposes DREAM-CIM, a digital SRAM-based computation-in-memory (CIM) accelerator. It targets an energy- and area-efficient implementation of the multiply-and-accumulate (MAC) operation, which is the core operation of neural networks. The accelerator is based on a multi-sub-array macro to increase parallelism, integrates multiplication operations within the memory cells such that they are executed while reading the cells, makes use of pipelining to further optimize the throughput of the MAC operations, and gets rid of the expensive adder-tree structures commonly used in State-of-The-Art (SOTA) digital CIM solutions by replacing them with a custom accumulation circuit to reduce power and area. The SPICE simulation results of the DREAM-CIM accelerator show an energy efficiency of 5097 TOPS/W (normalized to a 1-bit × 1-bit MAC operation) and an area efficiency of 3854 TOPS/mm$^2$ using 22 nm technology node.
The obtained circuit-level results were fed into a python-based system-level simulator to benchmark the system architecture using two applications, i.e., image classification (using MNIST and CIFAR-10 dataset on LeNet5 and Resnet-20 models) and object detection (using COCO dataset on the YoloV6 model). The system-level results show that DREAM-CIM can achieve an energy efficiency of 0.1mJ, 0.2mJ, and 11.02mJ per inference for the MNIST, YOLOv6, and CIFAR-10 datasets, respectively, while maintaining SOTA accuracy.

In recent years, Spin Waves (SWs) have emerged as a promising CMOS alternative technology, and SW interference-based majority gates have been proposed and experimentally realized. In this paper, we pursue a different computation avenue and introduce a SW device able to evaluate 2×2 2D convolution, which is a fundamental element for the implementation of Convolutional Neural Networks (CNNs). Assuming that the window pixels are P = [p₁, p₂; p₃, p₄] and the kernel is K = [k₁, k₂; k₃, k₄] we introduce a device which evaluates the convolution result Σ_{i = 1}⁴ p_i k_i within the SW domain by leveraging SWs inherent mechanisms, i.e., information encoding in SW amplitude and phase, SW amplitude decay due to Gilbert damping, SW interference. After introducing the SW device structure we demonstrate its proper behaviour by means of micromagnetic simulations. We also present power consumption, area, and delay estimates and argue that due to the fact that our proposal does not rely on standard adders and multipliers, it can substantially outperform traditional CMOS-based convolution implementations.

Timely identification of cardiac arrhythmia (abnormal heartbeats) is vital for early diagnosis of cardiovascular diseases. Wearable healthcare devices facilitate this process by recording heartbeats through electrocardiogram (ECG) signals and using AI-driven hardware to classify them into arrhythmia classes. Spiking neural networks (SNNs) are well-suited for such hardware as they consume low energy due to event-driven operation. However, their energy-efficiency and accuracy are constrained by encoding methods that translate real-valued ECG data into spikes. In this paper, we present an SNN-based ECG classification architecture featuring a new adaptive multi-threshold spike encoding scheme. This scheme adjusts encoding window and granularity based on the importance of ECG data samples, to capture essential information with fewer spikes. We develop a high-accuracy SNN model for such spike representation, by proposing a technique specifically tailored to our encoding. We design a hardware architecture for this model, which incorporates optimized layer post-processing for energy-efficient data-flow and employs fixed-point quantization for computational efficiency. Moreover, we integrate this architecture with our encoding scheme into a system-on-chip implementation using TSMC 40 nm technology. Our approach provides up to 5.1x energy-efficiency compared to state-of-the-art SNN-based ECG classifiers, with high accuracy.

In this paper, we introduce a novel passive physical anti-tampering Physical Unclonable Function (PUF) based on glitters that can protect an entire Integrated Circuit (IC) and/or Printable Circuit Board (PCB). A prototype of the proposed glitter based PUF has been developed. The glitters are dropped randomly in a resin layer during its formation and their positioning is used as the basis of a PUF. The PUF response is created by taking a picture inside the coating layer. To get a stable response resilient against noise and different temperature cycles, the picture is processed using filtering, image processing, and error correction. Using actual drill measurements, our findings indicate that even drilling with a 0.1mm diameter drill can be detected and lead to a wrong PUF response.