Computation-in-Memory (CIM) architectures address the rising demand for energy-efficient artificial intelligence (AI) solutions, by minimizing costly data movements between memory and processor. Within such architectures, SRAM-based digital CIM is especially attractive as it preserves the advantages of CIM while avoiding analog complexity. Recent studies have revealed potential weaknesses in these architectures, particularly to power side-channel attacks (SCA) capable of extracting sensitive model parameters (e.g., neural network (NN) weights), which represent the intellectual property of CIM-based neural network systems. In this study, we propose and evaluate two countermeasures to secure SRAM-based CIM architectures against power attacks: (1) Balanced Obfuscated-path countermeasure, and (2) Glitch Aware countermeasure. To validate their effectiveness, we conducted a comprehensive power analysis that successfully demonstrated attacks against an unprotected implementation. Our experimental results demonstrate that both countermeasures significantly improve resistance to power attacks. Although the Balanced Obfuscated-path offers better area overhead and run-time performance, the Glitch Aware approach achieves higher protection against advanced attacks, making each suitable for different design constraints.

The increasing complexity of semiconductor technologies is exposing limitations in traditional manufacturing test methodologies. Although fault-model-based testing has enabled efficient production screening for decades, growing evidence from advanced logic and memory technologies indicates that many realistic defect mechanisms are insufficiently represented by conventional fault abstractions, leading to test escapes and in-field failures. This paper examines three directions for improving outgoing product quality. First, we discuss the growing mismatch between fault models and actual silicon behavior and emphasize the need for silicon-informed assessment of defect coverage. Second, we investigate timing failures caused by process-variation-induced delay marginalities, which increasingly evade conventional scan-based delay testing. Finally, we present Device-Aware Test (DAT), a defect-centric methodology that derives fault models and test solutions directly from physical defect behavior. Examples from STT-MRAM, RRAM, and FeFET memories demonstrate how DAT enables the detection of realistic defect mechanisms beyond the reach of conventional approaches. Together, these directions support a transition toward defect-aware, data-driven testing for future semiconductor systems.

Vector–matrix multiplication (VMM), implemented through multiply–accumulate (MAC) operations, represents the dominant computational primitive in many artificial intelligence (AI) workloads. When executed on conventional von Neumann architectures, VMM operations suffer from important energy consumption and latency due to the separation between memory and processing units. To overcome these limitations, crossbar arrays built from Resistive Random Access Memory (RRAM) cells have been proposed for accelerating VMM computations. In this work, we investigate the key optimization trade-offs associated with implementing RRAM-based neural networks for classification applications. A simple two-layer neural network is first defined and trained in software to generate the weight matrices and bias parameters. Next, three hardware implementation scenarios are evaluated depending on whether negative floating-point numbers are used: Positive Weights Only (PWO), Positive and Negative Weights Only (PNWO), and Positive and Negative Weights with Biases (PNWB). The different implementations are analyzed at the hardware level by examining classification accuracy, energy efficiency, latency, and area overhead. The study further incorporates important RRAM limitations, including restricted conductance range and device variability. Hardware results show that the PWO scenario offers the lowest energy consumption (189 fJ/MAC) and area overhead but results in the lowest accuracy. PNWO and PNWB significantly improve accuracy (+177% and +180%) but increase energy consumption (+63% and +87%) and area (×2 and ×2.1). Under variability effects, PWO achieves better accuracy (94.65%), followed by PNWO (93.11%) and PNWB (92.11%).

Analog Compute-in-Memory (CIM), leveraging non-volatile memristive devices to perform in-place computations in the analog domain, holds great potential to efficiently accelerate vector-matrix multiplications (VMM) and realize AI (Artificial Intelligence) at the edge. However, the data converters in such architectures often trade-off accuracy for high energy and area overheads, practically limiting the benefits of CIM. In this work, we present SABCIM, an array-periphery co-design approach for CIM that enables accurate computation as well as digitization of analog VMM outputs with high energy efficiency and competitive area overhead. By leveraging complementary input activations and data storage, each crossbar column generates differential analog output corresponding to the vector-vector multiplication (VVM) result, while inherently addressing underlying non-idealities. This is digitized using a compact, dual-ramp voltage-to-time converter (VTC)-based analog-to-digital converter (ADC). Benchmark results indicate that our work achieves up to 19.6 × higher energy efficiency compared to state-of-the-art (SOTA), while maintaining comparable accuracies.

Resistive Random Access Memory (RRAM) has emerged as a promising candidate to succeed conventional memory technologies, offering advantages such as low energy operation and scalable storage density. As different manufacturers continue to advance RRAM toward large-scale production and commercial deployment, the demand for accurate and efficient testing methodologies becomes increasingly critical. This paper investigates interconnect and contact defects in RRAM arrays, with particular attention to the influence of the Data Background (DB), and proposes corresponding test strategies. A comprehensive defect space covering interconnect and contact defects is formulated for a layout-independent RRAM design. Systematic defect injection and circuit-level simulations are conducted to derive fault models, encompassing not only single-cell and two-cell coupling faults but also multi-cell faults strongly affected by DBs. The analysis identifies previously unreported 3-cell and 4-cell faults, which originate from defect-related sneak paths in the array. Conventional RRAM test schemes are unable to detect such faults. To address this limitation, a DB-aware test generation scheme is presented, capable of efficiently identifying all the aforementioned fault types and thereby enhancing the overall fault and defect coverage in RRAM devices.

RRAM-based compute-in-memory (CIM) AI accelerators integrate memory cells with mixed-signal peripherals to enable energy-efficient, low-latency edge computing. These architectures require novel test techniques for unique electrical defects. Current system-level functional tests cannot guarantee defect-free circuits, while accurate circuit-level techniques remain non-scalable to Deep Neural Networks (DNNs). To bridge this gap, we present the first structural test methodology for CIM DNNs, unifying system-level analysis with circuit-level precision. We accurately model RRAM crossbar defects to formulate test patterns, and then propagate results across layers for comprehensive structural testing. Generated test patterns are optimized either for 96% defect coverage or test time reduction by a factor of three while covering all unique defects and maintaining over 73% defect strength coverage.

The Computing-In-Memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck that limits conventional Von Neumann architectures. By performing data processing at the same physical location where the data are stored, CIM-based architectures minimize costly data movement and drastically improve energy efficiency. When implemented with Ferroelectric Field Effect Transistors (FeFETs), additional advantages from the non-volatility, fast switching, and low operating voltage of FeFETs are added. However, the widespread adoption of FeFETs is limited by their poor endurance, which is overcome by a Back End of the Line (BEoL) integration of FeFET-2, where a ferroelectric capacitor (FeCAP) is wired to the gate of a CMOS transistor providing high endurance compatible with low-power edge applications. These properties enable dense, low-power, and high-speed matrix operations essential for AI workloads. As a result, FeFET-2-based CIM accelerators offer a promising solution for energy-efficient, high-performance AI at the edge. The Ferro4EdgeAI project aims to develop an ultra low-power, scalable edge accelerator for AI, targeting a significant gain in energy efficiency with respect to state-of-the-art AI hardware accelerators. To attain this, our project focuses on innovation all along the value chain from materials, physic concepts, device architecture, integration technologies, and accelerators in a holistic design space exploration approach.

Physics-based compact models for emerging non-volatile memories (NVMs) are often limited by the complex interactions of microscopic domains and defects that are difficult to capture analytically, resulting in reduced accuracy and simulation efficiency. To address this challenge, a machine learning (ML)-based approach is proposed using artificial neural networks (ANNs) trained entirely on device measurement data, enabling a direct translation of fabrication characteristics into SPICE-compatible circuit models. The resulting models achieve high accuracy (MSE: 0.724, adjusted R² : 0.998), significantly outperforming physics-based baselines with an 18× lower MSE for polarization and a two-order-of-magnitude precision improvement in FeFET current simulation, while accurately capturing the wake-up process. Furthermore, the model demonstrates robust out-of-distribution (OOD) extrapolation to unseen ferroelectric thicknesses and a 33.7% improvement in simulation speed. These results validate the ML-based approach as a highly efficient, SPICE-compatible solution for next-generation memory.

Power side-channel attacks pose a serious threat to cryptographic hardware implementations. To avoid deploying insecure implementations, it is essential to perform side-channel leakage assessments at the pre-silicon stage. Register Transfer Level (RTL)-level or gate-level power traces-generated, for example using SpyGlass, can be produced very efficiently but suffer from limited accuracy. In contrast, post-layout simulations provide a much higher accuracy but are prohibitively time-consuming. In this work, we propose a hybrid approach that extracts layout information, including timing and parasitic effects, and augments the gate-level netlist with this data. This approach enables fast pre-silicon power trace generation that accurately embeds post-layout parasitics. Our results show that power traces generated from gate-level and transistor-level simulations, both augmented with layout information, perform similarly in key-ranking anlysis and have a low Euclidean distance, while the gate-level simulations are 19 x-125 x faster to generate.

Theoretically speaking, Majority logic, originally proposed in the ^{\prime }70s, enables more compact and efficient arithmetic implementations than the conventional Boolean counterpart. Nonetheless, CMOS technology based Majority logic realizations remain challenging, as standard transistor-based approaches are unable to directly exhibit majority behavior. However, recent exploration on beyond CMOS technologies created a resurgence of the interest in majority logic. In this work, we propose and analyze a novel approach towards the 3-input Majority gate (MAJ3) implementation by means of piezoelectric materials. By leveraging their intrinsic electromechanical properties, we convert the digital input signals into mechanical deformations, which are accumulated in a transfer layer. Subsequently, we transform the combined deformation back to the electric domain with a piezoelectronics element properly designed to perform majority functionality. We first present the underlying principles behind our proposal with a short introduction on majority logic, piezoelectronics, and the utilized simulation framework. Afterwards we introduce the proposed piezoelectric 3-input Majority gate (piezo-MAJ3) and strategies for optimizing its behavior and performance. We also detail the material parameters and structural design impact on device performance by utilizing both analytical discussion and physics-based simulations. Finally, we shortly highlight how our proposal can be directly integrated into CMOS circuits and compare the piezo-MAJ3 potential cost and performance with the ones of state of the art implementations. Our results indicate that when compared with its CMOS counterpart, the piezo-MAJ3 gate requires half the area, it is 7x faster, while reducing with 44% the energy consumption.

Although offering great potential for energy-efficient edge-AI, memristor-based CIM accelerators are severely hindered by IR drop induced errors. To tackle this, we propose a low-cost mitigation technique by first quantifying the impact of IR drop on the accuracy. Then, a mitigation strategy is developed to compensate for IR drop-induced inference accuracy reduction by combining an optimized mapping scheme with a fine-tuned calibration of the ADC. Results show the proposed solution can effectively mitigate IR drop with a negligible overhead.