Memristors are an emerging technology that enables artificial intelligence (AI) accelerators with high energy efficiency and radiation robustness — properties that are vital for the deployment of AI on-board spacecraft. However, space applications require reliable and precise computations, while memristive devices suffer from non-idealities, such as device variability, conductance drifts, and device faults. Thus, porting neural networks (NNs) to memristive devices often faces the challenge of severe performance degradation. In this work, we show in simulations that memristor-based NNs achieve competitive performance levels on on-board tasks, such as navigation & control and geodesy of asteroids. Through bit-slicing, temporal averaging of NN layers, and periodic activation functions, we improve initial results from around 0.07 to 0.01 and 0.3 to 0.007 for both tasks using RRAM devices, coming close to state-of-the-art levels (0.003−0.005 and 0.003, respectively). Our results demonstrate the potential of memristors for on-board space applications, and we are convinced that future technology and NN improvements will further close the performance gap to fully unlock the benefits of memristors.

Addressing non-idealities in Resistive Random Access Memories (RRAMs) is crucial for their successful commercialization. For example, the inherent resistance drift that occurs during consecutive read operations can induce Read Disturb Faults (RDF), leading to functional errors. This paper analyzes and characterizes the resistance drift and the RDF based on data measurements and presents a physics-based RRAM compact model that incorporates these non-idealities. Additionally, an in-field mitigation scheme is proposed, leveraging bidirectional read operations to balance the resistance. The scheme is implemented and validated through circuit simulations, both for RRAM used as memory and for RRAM-based computation-in-memory microarchitectures for deep neural networks. The results demonstrate that RRAM without any mitigation scheme can start failing after 8,000 consecutive reads, while our mitigation scheme ensures that the memory remains functional even after 10⁶ consecutive reads. Furthermore, the results indicate that using the MNIST dataset as a case study, the accuracy can drop significantly from 86% to as low as 12.5% without any mitigation scheme. In contrast, the proposed mitigation scheme improves this accuracy up to 84.2%.

Compute-in-memory (CIM) AI accelerators using non-volatile memories like RRAM enable energy-efficient edge inference by executing Multiply-Accumulate (MAC) operations directly in memory in a single cycle. These designs modify memory cells and analog-to-digital converters (ADCs), introducing faults not seen in standard memories. We present the first structural testing methodology and framework for RRAM-based CIM MAC circuits, including defect and fault models for memory cells and ADCs. Our robust inference-driven tests exercise full MAC functionality, significantly reducing test time compared to traditional methods, and integrating cell and peripheral testing to ensure high reliability, defect coverage, and operational efficiency.

Resistive Random-Access Memories (ReRAMs) represent a promising candidate to complement and/or replace CMOS-based memories adopted in several emerging applications. Despite all their advantages – mainly CMOS process compatibility, zero standby power, and high scalability and density – the use of ReRAMs in real applications depends on guaranteeing their quality after manufacturing. As observed in CMOS-based memories, ReRAMs are also susceptible to manufacturing deviations, including defects and process variations, that can cause faulty behaviors different from those observed in CMOS technology, increasing not only the manufacturing test complexity but also the time required to perform the test. In this context, this paper proposes to study the use of temperature to facilitate fault propagation in ReRAMs, reducing the required test time. A case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library was adopted. During the proposed study, a total of 17 defects were injected in different positions of the ReRAM cell, and their respective faulty behavior was classified into conventional and unique faults, considering three different temperatures (25, 100, and -40 °C). The obtained results show that the temperature can, depending on the position of the defect, facilitate fault propagation, which reduces the time required for performing manufacturing testing.

The development of Ferroelectric Field-Effect Transistor (FeFET) manufacturing requires high-quality test solutions, yet research on FeFET testing is still in a nascent stage. To generate a dedicated test method for FeFETs, it is critical to have a deep understanding of manufacturing defects and accurately model them. In this work, we introduce the unique defect, Anomalous Charge Trapping (ACT), in FeFETs. The ACT-defective FeFET is characterized, and the physical mechanism of the defect is explained. Then, we apply the Deviceaware Test (DAT) method to design a specific ACT-defective FeFET model, which includes the physical impact of the defect on the electrical parameters of defect-free models, and calibrate the model with measurement data. Fault modeling is performed based on circuit-level simulations, and dedicated test solutions are proposed.

Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) technologies, especially in embedded systems and edge computing. However, due to their physical characteristics, FeFETs exhibit unique defects—such as Threshold Voltage Shifting (TVS) caused by trap charges in the oxide layer—that are not captured by conventional defect models. This study adopts the Device-Aware Test (DAT) methodology to model these defects by incorporating their impact into the electrical parameters, calibrated using measurement data. Defect injection, circuit-level simulations, and fault analysis are performed to derive realistic fault models. Finally, the March algorithm and Design-for-Test (DfT) techniques are proposed to effectively detect these defects.

Edge AI accelerators have revolutionized intelligent information processing, enabling applications, such as self-driving cars and low-power IoT devices. Design efforts prioritize computational power and energy efficiency. Nevertheless, testability is also critical for in-field, reliable operation, especially for novel architectures such as memristive, analog Computation-in-Memory (CIM) cores. These structures combine emerging Resistive Random Access Memory (RRAM) with CMOS peripherals to efficiently implement vector-matrix-multiplication (VMM) operations for inference. Current research on AI Accelerator testing relies on functional test patterns, derived from abstract and unrealistic fault models. This paper presents a novel structural testing methodology for CIM VMM circuits. The methodology utilizes device-level defect models and defines new fault models for CIM VMM. The resulting test patterns are optimized to maximize defect coverage and minimize test time, since they require only a single write operation per victim cell.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team's section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

While Resistive RRAM (RRAM) provides appealing features for artificial neural networks (NN) such as low power operation and high density, its conductance variation can pose significant challenges for synaptic weight storage. This paper reports an experimental evaluation of the conductance variations of manufactured RRAMs memory cells at the memory array level. Variability is evaluated with respect to the RRAM low resistance state (LRS) and high resistance state (HRS) conductance ratio. This ratio is selected as the parameter of interest as it guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell is in storing and retrieving data. The measurement results show that conductance ratio is significantly influenced by variability. Using these findings, the performance of an artificial neural network that uses individual RRAM cells for synaptic weight storage is evaluated in relation to conductance variability. It is shown that RRAM variability can heavily affect the network behavior, resulting in a substantial decrease in the classification accuracy during inference.

Resistive Random Access Memories (RRAMs) are now undergoing commercialization, with substantial investment from many semiconductor companies. However, due to the immature manufacturing process, RRAMs are prone to exhibit unique defects, which should be efficiently identified for high-volume production. Hence, obtaining diagnostic solutions for RRAMs is necessary to facilitate yield learning, and improve RRAM quality. Recently, the Device-Aware Test (DAT) approach has been proposed as an effective method to detect unique defects in RRAMs. However, the DAT focuses more on developing defect models to aid production testing but does not focus on the distinctive features of defects to diagnose different defects. This paper proposes a Device-Aware Diagnosis method; it is based on the DAT approach, which is extended for diagnosis. The method aims to efficiently distinguish unique defects and conventional defects based on their features. To achieve this, we first define distinctive features of each defect based on physical analysis and characterizations. Then, we develop efficient diagnosis algorithms to extract electrical features and fault signatures for them. The simulation results show the effectiveness of the developed method to reliably diagnose all targeted defects.

Resistive Random Access Memories (RRAMs) are now undergoing commercialization, with substantial investment from many semiconductor companies. However, due to the immature manufacturing process, RRAMs are prone to exhibit new failure mechanisms and faults, which should be efficiently detected for high-volume production. Some of those faults are hard-to-detect, and require specific Design-for-Testability (DfT) circuit design. This paper proposes a DfT based on a parallel-reference write circuit that can detect all single-cell RRAM array faults: strong faults (directly causing logic errors) as well as weak faults (caused by parametric deviations). The scheme replaces the regular write driver, and enables the monitoring and comparison of the write current against multiple references during a single write operation. Hence, it serves as a DfT scheme and as a normal write circuit simultaneously. In addition, it enhances production testing speed and online fault detection, while keeping the area overhead low. Furthermore, the DfT is configurable for efficient diagnosis and yield learning. The results of the simulations performed do not only show that the DfT can detect single-cell conventional faults (due to interconnects and contacts) as well as unique RRAM faults (based on silicon data) that have been demonstrated to exist, but also that the DfT is robust to process variations.

Traditional charge-based memories such as dynamic RAM (DRAM) and flash are facing more and more manufacturing, reliability, energy, and speed issues. A growing group of emerging memory technologies, such resistive RAM (RRAM), spin-transfer torque magnetic RAM (STT-MRAM), phase change memory (PCM), and Ferroelectric (Fe) devices (e.g., FeFET, FeRAM), address these problems. Nonetheless, these technologies are also not perfect, and thus special care must be taken to ensure that the lifecycle management, from design to obsolescence, of these memories is as optimal as possible. Lifecycle management is being developed for traditional technologies, but these are not optimized for emerging memories yet. In this paper, we present the first steps of lifecycle management for emerging memories. We analyze the different lifecycle phases that exist for two case studies on RRAM and FeFET-based memories. In this analysis, we identify how the phases affect each other and which optimizations are possible by analyzing the complete lifecycle. Finally, we compare the lifecycle phases of these two emerging memories to see how a unified approach can be developed.

Resistive Random-Access Memories (ReRAMs) represent a promising candidate to complement and/or replace CMOS-based memories used in several emerging applications. Despite all the advantages of using these novel memories, mainly due to the memristive device's CMOS manufacturing process compatibility, zero standby power consumption, as well as, high scalability and density, the use of them in real applications depends on being able to guarantee their quality after manufacturing. As observed in CMOS-based memories, ReRAMs are also susceptible to manufacturing deviations, defects, and process variations, that can cause faulty behaviors different from the ones observed in CMOS technology, increasing not only the manufacturing test complexity but also the time required to perform the test. In this context, this paper proposes to study the use of temperature to facilitate fault propagation in ReRAMs, reducing the required test time. A case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library was adopted. During the proposed study, a total of 17 defects were injected in different positions of the ReRAM cell, and their respective faulty behavior was classified into traditional and unique faults, considering three temperatures (25, 100, and -40°C). The obtained results show that the temperature can, depending on the position of the defect, facilitate fault propagation, which reduces the time required for performing manufacturing testing.

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

While Resistive RRAM (RRAM) offers attractive features for artificial neural networks (NN) such as low power operation and high-density, its conductance variation can pose significant challenges when the storage of synaptic weights is concerned. This paper reports an experimental evaluation of the conductance variations of manufactured RRAMs at the memory array level. Working at the memory array level allows to catch cycle-to-cycle (C2C) as well as device-to-device (D2D) variability and, hence, to propose a realistic evaluation of the conductance variation. Variability is evaluated with respect to the RRAM low resistance state (LRS) and high resistance state (HRS) conductance ratio. This ratio is selected as the parameter of interest as it guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell is in storing and retrieving data. The measurement results show that the conductance ratio is heavily affected by variability. Large spatial and temporal variations are reported, making challenging RRAM-based analog weight storage.

Due to the immature manufacturing process, Resistive Random Access Memories (RRAMs) are prone to exhibit new failure mechanisms and faults, which should be efficiently detected for high-volume production. Those unique faults are hard to detect but require specific Design-for-Test (DfT) circuit design. This paper proposes a DfT based on a parallel-reference write circuit that can detect all RRAM array faults during diagnosis, production testing, and its application in the field.

As electronics and software become more integrated into automobiles, Functional Safety (FuSa) per ISO 26262 becomes important. It assesses the risk level of automotive chips, reflected by the Automotive Safety Integrity Level (ASIL). Fault injection simulation verifies the FuSa of a design by injecting faults and classifying them based on whether safety mechanisms detect them. Discrepancies in classification results from FuSa EDA tools can lead to varying ASIL assignments and misrepresent associated risk. Thus, we evaluate two FuSa EDA tools, Cadence® XFS and Synopsys® VC Z01X, for RTL designs. We find that the fault space covered by the tools is not complete. Hence, we propose a novel verification methodology combining both tools to achieve maximum fault space coverage. We apply this approach to the AutoSoC benchmark suite and achieve a more accurate Diagnostic Coverage (DC) of 97.79%, over the baseline verification methodology of 98.36%, at the cost of injecting 1.31 times more faults. Our work ensures that the correct ASIL level is assigned through accurate DC estimation.

As emerging non-volatile memory (NVM) devices, Ferroelectric Field-Effect Transistors (FeFETs) present distinctive opportunities for the design of ultra-dense and low-leakage memory systems. For matured FeFET manufacturing, it is extremely important to have an understanding of manufacturing defects and accurately model them to develop effective test solutions. This paper introduces a comprehensive framework for defect and fault modeling, which enables the development of test solutions. First, a classification of FeFET manufacturing defects is provided; both conventional defects (such as contacts and interconnect defects) as well as unique FeFET defects are discussed. The latter FeFET specific defect leads to unique faults that cannot be adequately described using traditional modeling approaches. Then, the Device-Aware Test (DAT) method is used to effectively and appropriately model, analyze and develop test solutions for such unique defects; the approach will be illustrated for Stuck-at-Polarization (SAP) defects.

The Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is on its way to commercialization. However, the development of high-quality test solutions for STT-MRAMs poses challenges due to the specific working mechanism of the core element of the STT-MRAM bit cells, i.e., the magnetic tunnel junction (MTJ), which involves both a magnetic field and spin-transfer torque. This property can introduce defects unique to MTJs which may escape from test programs that consist solely of functional write and read operations, like march tests. Hence, it is important to develop test solutions that go beyond conventional march tests. This paper explores the effect of applying an external magnetic field (H_ext) on the test quality and test time of STT-MRAMs, which could be achieved by integrating one or more magnets in the Automated Test Equipment (ATE) setup. A framework for these so-called H_ext-assisted tests is presented and implemented for all known conventional and unique defects. The paper demonstrates that the H_ext-assisted tests offer superior coverage and/or lower test time compared to regular functional tests, like march tests. The effectiveness of these tests are validated through silicon measurements.

Guaranteeing high-quality test solutions for Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a must to speed up its high-volume production. A high test quality requires maximizing the fault coverage. Detecting permanent faults is relatively simple compared to intermittent faults; the latter are faults (caused by non-environmental conditions) that appear and disappear as a function of time, and are therefore hard to detect. Testing for such faults in STT-MRAMs is even worse considering the Magnetic Tunneling Junction inherent property ‘intrinsic switching stochasticity’, which results in inevitable random write errors. This paper presents a novel Design-for-Testability (DFT) scheme for detecting intermittent faults in STT-MRAMs; it is based on monitoring the write current. The strength of the write current is inversely correlated to the write error rate; when the write current is smaller than the specification, the device is considered faulty. A reduction in the write current can be caused by any defect in the write path of the memory (e.g., interconnects and contacts). Simulation results based on industrial design show that applying DFT yields a superior coverage of intermittent faults compared to functional test methods, such as march tests.