Combined Array and ADC Structural Test for RRAM-based Multiply-and-Accumulate Circuits

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Combined Array and ADC Structural Test for RRAM-based Multiply-and-Accumulate Circuits

Conference Paper (2025)

Author(s)

E.A. Serlis (TU Delft - Computer Engineering)

H. Xun (TU Delft - Computer Engineering)

E. Arapidis (TU Delft - Computer Engineering)

Anteneh Gebregiorgis (TU Delft - Computer Engineering)

M. Taouil (CognitiveIC, TU Delft - Computer Engineering)

S. Hamdioui (CognitiveIC, TU Delft - Computer Engineering)

M. Fieback (TU Delft - Computer Engineering)

Research Group

Computer Engineering

DOI related publication

https://doi.org/10.1109/ITC58126.2025.00076

Computation-in-memory RRAMs Structural test Multiply-and-accumulate

To reference this document use:

https://resolver.tudelft.nl/uuid:df21ceba-e423-409e-90e8-f55f955cb7d1

More Info

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Publication Year

2025

Language

English

Research Group

Computer Engineering

Bibliographical Note

Green Open Access added to TU Delft Institutional Repository as part of the Taverne amendment. More information about this copyright law amendment can be found at https://www.openaccess.nl. Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.@en

Pages (from-to)

506-509

ISBN (print)

979-8-3315-7042-2

ISBN (electronic)

979-8-3315-7041-5

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Abstract

Compute-in-memory (CIM) AI accelerators using non-volatile memories like RRAM enable energy-efficient edge inference by executing Multiply-Accumulate (MAC) operations directly in memory in a single cycle. These designs modify memory cells and analog-to-digital converters (ADCs), introducing faults not seen in standard memories. We present the first structural testing methodology and framework for RRAM-based CIM MAC circuits, including defect and fault models for memory cells and ADCs. Our robust inference-driven tests exercise full MAC functionality, significantly reducing test time compared to traditional methods, and integrating cell and peripheral testing to ensure high reliability, defect coverage, and operational efficiency.

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