Resistive Random Access Memory (RRAM) has emerged as a promising candidate to succeed conventional memory technologies, offering advantages such as low energy operation and scalable storage density. As different manufacturers continue to advance RRAM toward large-scale production and commercial deployment, the demand for accurate and efficient testing methodologies becomes increasingly critical. This paper investigates interconnect and contact defects in RRAM arrays, with particular attention to the influence of the Data Background (DB), and proposes corresponding test strategies. A comprehensive defect space covering interconnect and contact defects is formulated for a layout-independent RRAM design. Systematic defect injection and circuit-level simulations are conducted to derive fault models, encompassing not only single-cell and two-cell coupling faults but also multi-cell faults strongly affected by DBs. The analysis identifies previously unreported 3-cell and 4-cell faults, which originate from defect-related sneak paths in the array. Conventional RRAM test schemes are unable to detect such faults. To address this limitation, a DB-aware test generation scheme is presented, capable of efficiently identifying all the aforementioned fault types and thereby enhancing the overall fault and defect coverage in RRAM devices.

Vector–matrix multiplication (VMM), implemented through multiply–accumulate (MAC) operations, represents the dominant computational primitive in many artificial intelligence (AI) workloads. When executed on conventional von Neumann architectures, VMM operations suffer from important energy consumption and latency due to the separation between memory and processing units. To overcome these limitations, crossbar arrays built from Resistive Random Access Memory (RRAM) cells have been proposed for accelerating VMM computations. In this work, we investigate the key optimization trade-offs associated with implementing RRAM-based neural networks for classification applications. A simple two-layer neural network is first defined and trained in software to generate the weight matrices and bias parameters. Next, three hardware implementation scenarios are evaluated depending on whether negative floating-point numbers are used: Positive Weights Only (PWO), Positive and Negative Weights Only (PNWO), and Positive and Negative Weights with Biases (PNWB). The different implementations are analyzed at the hardware level by examining classification accuracy, energy efficiency, latency, and area overhead. The study further incorporates important RRAM limitations, including restricted conductance range and device variability. Hardware results show that the PWO scenario offers the lowest energy consumption (189 fJ/MAC) and area overhead but results in the lowest accuracy. PNWO and PNWB significantly improve accuracy (+177% and +180%) but increase energy consumption (+63% and +87%) and area (×2 and ×2.1). Under variability effects, PWO achieves better accuracy (94.65%), followed by PNWO (93.11%) and PNWB (92.11%).

Computation-in-Memory (CIM) architectures address the rising demand for energy-efficient artificial intelligence (AI) solutions, by minimizing costly data movements between memory and processor. Within such architectures, SRAM-based digital CIM is especially attractive as it preserves the advantages of CIM while avoiding analog complexity. Recent studies have revealed potential weaknesses in these architectures, particularly to power side-channel attacks (SCA) capable of extracting sensitive model parameters (e.g., neural network (NN) weights), which represent the intellectual property of CIM-based neural network systems. In this study, we propose and evaluate two countermeasures to secure SRAM-based CIM architectures against power attacks: (1) Balanced Obfuscated-path countermeasure, and (2) Glitch Aware countermeasure. To validate their effectiveness, we conducted a comprehensive power analysis that successfully demonstrated attacks against an unprotected implementation. Our experimental results demonstrate that both countermeasures significantly improve resistance to power attacks. Although the Balanced Obfuscated-path offers better area overhead and run-time performance, the Glitch Aware approach achieves higher protection against advanced attacks, making each suitable for different design constraints.

RRAM-based compute-in-memory (CIM) AI accelerators integrate memory cells with mixed-signal peripherals to enable energy-efficient, low-latency edge computing. These architectures require novel test techniques for unique electrical defects. Current system-level functional tests cannot guarantee defect-free circuits, while accurate circuit-level techniques remain non-scalable to Deep Neural Networks (DNNs). To bridge this gap, we present the first structural test methodology for CIM DNNs, unifying system-level analysis with circuit-level precision. We accurately model RRAM crossbar defects to formulate test patterns, and then propagate results across layers for comprehensive structural testing. Generated test patterns are optimized either for 96% defect coverage or test time reduction by a factor of three while covering all unique defects and maintaining over 73% defect strength coverage.

The increasing complexity of semiconductor technologies is exposing limitations in traditional manufacturing test methodologies. Although fault-model-based testing has enabled efficient production screening for decades, growing evidence from advanced logic and memory technologies indicates that many realistic defect mechanisms are insufficiently represented by conventional fault abstractions, leading to test escapes and in-field failures. This paper examines three directions for improving outgoing product quality. First, we discuss the growing mismatch between fault models and actual silicon behavior and emphasize the need for silicon-informed assessment of defect coverage. Second, we investigate timing failures caused by process-variation-induced delay marginalities, which increasingly evade conventional scan-based delay testing. Finally, we present Device-Aware Test (DAT), a defect-centric methodology that derives fault models and test solutions directly from physical defect behavior. Examples from STT-MRAM, RRAM, and FeFET memories demonstrate how DAT enables the detection of realistic defect mechanisms beyond the reach of conventional approaches. Together, these directions support a transition toward defect-aware, data-driven testing for future semiconductor systems.

Physics-based compact models for emerging non-volatile memories (NVMs) are often limited by the complex interactions of microscopic domains and defects that are difficult to capture analytically, resulting in reduced accuracy and simulation efficiency. To address this challenge, a machine learning (ML)-based approach is proposed using artificial neural networks (ANNs) trained entirely on device measurement data, enabling a direct translation of fabrication characteristics into SPICE-compatible circuit models. The resulting models achieve high accuracy (MSE: 0.724, adjusted R² : 0.998), significantly outperforming physics-based baselines with an 18× lower MSE for polarization and a two-order-of-magnitude precision improvement in FeFET current simulation, while accurately capturing the wake-up process. Furthermore, the model demonstrates robust out-of-distribution (OOD) extrapolation to unseen ferroelectric thicknesses and a 33.7% improvement in simulation speed. These results validate the ML-based approach as a highly efficient, SPICE-compatible solution for next-generation memory.

Power side-channel attacks pose a serious threat to cryptographic hardware implementations. To avoid deploying insecure implementations, it is essential to perform side-channel leakage assessments at the pre-silicon stage. Register Transfer Level (RTL)-level or gate-level power traces-generated, for example using SpyGlass, can be produced very efficiently but suffer from limited accuracy. In contrast, post-layout simulations provide a much higher accuracy but are prohibitively time-consuming. In this work, we propose a hybrid approach that extracts layout information, including timing and parasitic effects, and augments the gate-level netlist with this data. This approach enables fast pre-silicon power trace generation that accurately embeds post-layout parasitics. Our results show that power traces generated from gate-level and transistor-level simulations, both augmented with layout information, perform similarly in key-ranking anlysis and have a low Euclidean distance, while the gate-level simulations are 19 x-125 x faster to generate.

Addressing non-idealities in Resistive Random Access Memories (RRAMs) is crucial for their successful commercialization. For example, the inherent resistance drift that occurs during consecutive read operations can induce Read Disturb Faults (RDF), leading to functional errors. This paper analyzes and characterizes the resistance drift and the RDF based on data measurements and presents a physics-based RRAM compact model that incorporates these non-idealities. Additionally, an in-field mitigation scheme is proposed, leveraging bidirectional read operations to balance the resistance. The scheme is implemented and validated through circuit simulations, both for RRAM used as memory and for RRAM-based computation-in-memory microarchitectures for deep neural networks. The results demonstrate that RRAM without any mitigation scheme can start failing after 8,000 consecutive reads, while our mitigation scheme ensures that the memory remains functional even after 10⁶ consecutive reads. Furthermore, the results indicate that using the MNIST dataset as a case study, the accuracy can drop significantly from 86% to as low as 12.5% without any mitigation scheme. In contrast, the proposed mitigation scheme improves this accuracy up to 84.2%.

While Resistive RRAM (RRAM) provides appealing features for artificial neural networks (NN) such as low power operation and high density, its conductance variation can pose significant challenges for synaptic weight storage. This paper reports an experimental evaluation of the conductance variations of manufactured RRAMs memory cells at the memory array level. Variability is evaluated with respect to the RRAM low resistance state (LRS) and high resistance state (HRS) conductance ratio. This ratio is selected as the parameter of interest as it guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell is in storing and retrieving data. The measurement results show that conductance ratio is significantly influenced by variability. Using these findings, the performance of an artificial neural network that uses individual RRAM cells for synaptic weight storage is evaluated in relation to conductance variability. It is shown that RRAM variability can heavily affect the network behavior, resulting in a substantial decrease in the classification accuracy during inference.

Resistive RAM (RRAM) design optimization and error monitoring is crucial for memory storage applications but also to enable future brain-inspired systems beyond the capabilities of today’s hardware. The figure-of-merit confirming the presence of resistive switching in RRAM devices is its resistance window expressed by the HRS/LRS ratio (High Resistance State over the Low Resistance State). This ratio guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell becomes in storing and retrieving data. From this perspective, this paper proposes an analysis of RRAM intermittent errors with respect to the RRAM resistance ratio. The impact of intermittent errors on the HRS/LRS ratio is analyzed at the RRAM cell electrical level using a dedicated test chip. Silicon measurements show that all detected RRAM intermittent errors directly result from resistance drifts due to ineffective programming operations. In view of these findings, intermittent error mitigation schemes are proposed to address these errors at the circuit level.