Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

Conference paper (2023)

Authors

S. Masoumian Intrinsic ID B.V., Computer Engineering - EEMCS
Roel Maes Intrinsic ID B.V.
Rui Wang Intrinsic ID B.V.
Karthik Keni Yerriswamy Intrinsic ID B.V.
Geert-Jan Schrijen Intrinsic ID B.V.
S. Hamdioui Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2023 S. Masoumian, Roel Maes, Rui Wang, Karthik Keni Yerriswamy, Geert-Jan Schrijen, S. Hamdioui, M. Taouil
DOI
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https://doi.org/10.1109/VLSI-SoC57769.2023.10321895
Bias Temperature FinFET SRAM PUF Power Supply Network
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Published Date

2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.