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Filip Bradarić
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Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and faults that cause functional errors. These faults cannot all be detected by state-of-the-art test and diagnosis solutions, thus leading to slower product development and low-quality products. This paper introduces a design-for-test (DFT) based on a parallel-multi-reference read (PMRR) circuit that can detect all RRAM array faults. The PMRR circuit replaces the standard sense amplifier and compares the cell’s state to multiple references during one read operation. Thus, it can be used as a DFT scheme and a normal read circuit at once. This allows for speeding up production testing and the online detection of faults. Furthermore, the circuit is extendable so that more references can be compared, which is required for efficient diagnosis. Finally, the references can be adjusted to maximize the production yield. The circuit outperforms state-of-the-art solutions because it can detect all RRAM faults during diagnosis, production testing, and during its application in the field while minimizing yield loss.
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Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and faults that cause functional errors. These faults cannot all be detected by state-of-the-art test and diagnosis solutions, thus leading to slower product development and low-quality products. This paper introduces a design-for-test (DFT) based on a parallel-multi-reference read (PMRR) circuit that can detect all RRAM array faults. The PMRR circuit replaces the standard sense amplifier and compares the cell’s state to multiple references during one read operation. Thus, it can be used as a DFT scheme and a normal read circuit at once. This allows for speeding up production testing and the online detection of faults. Furthermore, the circuit is extendable so that more references can be compared, which is required for efficient diagnosis. Finally, the references can be adjusted to maximize the production yield. The circuit outperforms state-of-the-art solutions because it can detect all RRAM faults during diagnosis, production testing, and during its application in the field while minimizing yield loss.
Conference paper
(2022)
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Abhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradarić, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui
Emerging non-volatile resistive RAM (RRAM) device technology has shown great potential to cultivate not only high-density memory storage, but also energy-efficient computing units. However, the unique challenges related to RRAM fabrication process render the traditional memory testing solutions inefficient and inadequate for high product quality. This paper presents low-cost design-for-testability (DFT) solutions that augment the testing process and improve the fault coverage. A computation-in-memory (CIM) based DFT is realized to expedite the detection and diagnosis of faults by developing logic designs involving multi-row activation. A novel addressing scheme is introduced to facilitate the diagnosis of faults. Reconfigurable logic designs are developed to detect unique RRAM faults that offer features such as programmable reference generations, period, and voltage of operation. DFT implementations are validated on a post-layout extracted platform and testing sequences are introduced by incorporating the proposed DFTs. Results show that more than 2.3× speedup and better coverage are achieved with 6× area reduction when compared with state-of-the-art solutions.
...
Emerging non-volatile resistive RAM (RRAM) device technology has shown great potential to cultivate not only high-density memory storage, but also energy-efficient computing units. However, the unique challenges related to RRAM fabrication process render the traditional memory testing solutions inefficient and inadequate for high product quality. This paper presents low-cost design-for-testability (DFT) solutions that augment the testing process and improve the fault coverage. A computation-in-memory (CIM) based DFT is realized to expedite the detection and diagnosis of faults by developing logic designs involving multi-row activation. A novel addressing scheme is introduced to facilitate the diagnosis of faults. Reconfigurable logic designs are developed to detect unique RRAM faults that offer features such as programmable reference generations, period, and voltage of operation. DFT implementations are validated on a post-layout extracted platform and testing sequences are introduced by incorporating the proposed DFTs. Results show that more than 2.3× speedup and better coverage are achieved with 6× area reduction when compared with state-of-the-art solutions.