Resistive Random Access Memories (RRAMs) are being commercialized with significant investment from several semiconductor companies. In order to provide efficient and high-quality test solutions to push high-volume production, a comprehensive understanding of manufacturing defects is significantly required. This paper identifies and characterizes the over-RESET phenomenon based on silicon measurements. In our case study, 30% cycles suffered from intermittent extremely high resistance state exceeding the high resistance state criteria. The paper shows the limitations of conventional defect modeling based on linear resistors. To address this challenge, the Device-Aware (DA) defect modeling method is applied; a model of the defective RRAM device is developed and calibrated using measurements to accurately describe the impact of the defect on the electrical behavior of the memory device. Afterward, fault analysis is performed based on the DA defect model, and appropriate fault models are introduced; they show that the DA defect model will sensitize deep (extremely high resistance) state faults. Finally, dedicated test solutions for over-RESET devices are proposed.@en

Many companies are heavily investing in the commercialization of Resistive Random Access Memories (RRAMs). This calls for a comprehensive understanding of manufacturing defects to develop efficient and high-quality test and diagnosis solutions to push high-volume production. This paper identifies and characterizes a new defect based on silicon measurements; the defect is called Ion Depletion (ID). In our case study, 45% cycles suffered from an intermittent reduction in high resistance state and did not impact low resistance state. The paper shows that the traditional fault modeling based on linear resistors as a defect model is not accurate. To address this challenge, the Device-Aware (DA) defect modeling method is applied; an RRAM model of the defective device is developed and calibrated using measurements to accurately describe the impact of the defect on the electrical behavior of the memory device. Afterward, fault analysis is performed based on the DA defect model, and appropriate fault models are introduced; they show that the ID defect may sensitize undefined state faults. Finally, dedicated test and diagnosis solutions for the ID defect are proposed.@en

Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) are on their way to commercialization. However, obtaining high-quality test and diagnosis solutions for STT-MRAMs is challenging due to the existence of unique defects in Magnetic Tunneling Junctions (MTJs). Recently, the Device-Aware Test (DA-Test) method has been put forward as an effective approach mainly for detecting unique defecting STT-MRAMs. In this study, we propose a further advancement based on the DA-Test framework, introducing the Device-Aware Diagnosis (DA-Diagnosis) method. This method comprises two steps: a) defining distinctive features of each unique defect by characterization and physical analysis of defective MTJs, and b) utilizing march algorithms to extract distinctive features. The effectiveness of the proposed approach is validated in an industrial setting with real devices and data measurement.@en

Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This paper analyzes interconnect and contact defects in RRAMs, while considering the impact of the memory Data Background (DB), and proposes test solutions. The complete interconnect and contact defect space in a layout-independent RRAM design is defined. Exhaustive defect injection and circuit simulation are performed in a systematic manner to derive appropriate fault models, not only for single-cell and two-cell coupling faults, but also for multi-cell coupling faults where the DBs are important. The results show the existence of unique 3-cell and 4-cell coupling faults due to e.g., the sneak path in the array induced by defects. These unique faults cannot be detected with traditional RRAM test solutions. Therefore, the paper introduces a test generation method that takes into account the DB, which is able to efficiently detect all these faults; hence, further improving the fault/defect coverage in RRAMs.@en

Resistive Random Access Memories (RRAMs) are now undergoing commercialization, with substantial investment from many semiconductor companies. However, due to the immature manufacturing process, RRAMs are prone to exhibit unique defects, which should be efficiently identified for high-volume production. Hence, obtaining diagnostic solutions for RRAMs is necessary to facilitate yield learning, and improve RRAM quality. Recently, the Device-Aware Test (DAT) approach has been proposed as an effective method to detect unique defects in RRAMs. However, the DAT focuses more on developing defect models to aid production testing but does not focus on the distinctive features of defects to diagnose different defects. This paper proposes a Device-Aware Diagnosis method; it is based on the DAT approach, which is extended for diagnosis. The method aims to efficiently distinguish unique defects and conventional defects based on their features. To achieve this, we first define distinctive features of each defect based on physical analysis and characterizations. Then, we develop efficient diagnosis algorithms to extract electrical features and fault signatures for them. The simulation results show the effectiveness of the developed method to reliably diagnose all targeted defects.@en

The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its fault models and test solutions. The BH defect causes MTJ state to oscillate during write operations, leading to write failures. The characterization of the defect is carried out based on manufactured MTJ devices. Due to the observed non-linear characteristics, the BH defect cannot be modelled with a linear resistance. Hence, device-aware defect modeling is applied by considering the intrinsic physical mechanisms; the model is then calibrated based on measurement data. Thereafter, the fault modeling and analysis is performed based on circuit-level simulations; new fault primitives/models are derived. These accurately describe the way the STT-MRAM behaves in the presence of BH defect. Finally, dedicated march test and a Design-for-Test solutions are proposed.@en