Characterization and Test of Intermittent Over RESET in RRAMs

Conference paper (2023)

Authors

H. Xun Computer Engineering - EEMCS
M. Fieback Computer Engineering - EEMCS
S. Yuan Computer Engineering - EEMCS
Hassen Aziza Aix Marseille Université
Thiago Copetti Rheinisch-Westfälische Technische Hochschule
Leticia Bolzani Poehls Rheinisch-Westfälische Technische Hochschule
M. Taouil CognitiveIC, Computer Engineering - EEMCS
S. Hamdioui CognitiveIC, Computer Engineering - EEMCS
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2023 H. Xun, M. Fieback, S. Yuan, Hassen Aziza, Mathijs Heidekamp, Thiago Copetti, Leticia Bolzani Poehls, M. Taouil, S. Hamdioui
DOI
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https://doi.org/10.1109/ATS59501.2023.10317990
Fault modeling RRAM test Device-aware defect model Design-for-Testability (DfT)
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Published Date

2023

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

Resistive Random Access Memories (RRAMs) are being commercialized with significant investment from several semiconductor companies. In order to provide efficient and high-quality test solutions to push high-volume production, a comprehensive understanding of manufacturing defects is significantly required. This paper identifies and characterizes the over-RESET phenomenon based on silicon measurements. In our case study, 30% cycles suffered from intermittent extremely high resistance state exceeding the high resistance state criteria. The paper shows the limitations of conventional defect modeling based on linear resistors. To address this challenge, the Device-Aware (DA) defect modeling method is applied; a model of the defective RRAM device is developed and calibrated using measurements to accurately describe the impact of the defect on the electrical behavior of the memory device. Afterward, fault analysis is performed based on the DA defect model, and appropriate fault models are introduced; they show that the DA defect model will sensitize deep (extremely high resistance) state faults. Finally, dedicated test solutions for over-RESET devices are proposed.