Device-Aware Test for Anomalous Charge Trapping in FeFETs
Sicong Yuan (TU Delft - Computer Engineering)
Changhao Wang (Politecnico di Torino)
M. Fieback (TU Delft - Computer Engineering)
Hanzhi Xun (TU Delft - Computer Engineering)
Mottaqiallah Taouil (TU Delft - Computer Engineering)
Xiuyan Li (Shanghai Jiao Tong University)
Danyang Chen (Shanghai Jiao Tong University)
Lin Wang (Shanghai Jiao Tong University)
Nicolo Bellarmino (Politecnico di Torino)
Riccardo Cantoro (Politecnico di Torino)
S. Hamdioui (TU Delft - Computer Engineering)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
The development of Ferroelectric Field-Effect Transistor (FeFET) manufacturing requires high-quality test solutions, yet research on FeFET testing is still in a nascent stage. To generate a dedicated test method for FeFETs, it is critical to have a deep understanding of manufacturing defects and accurately model them. In this work, we introduce the unique defect, Anomalous Charge Trapping (ACT), in FeFETs. The ACT-defective FeFET is characterized, and the physical mechanism of the defect is explained. Then, we apply the Deviceaware Test (DAT) method to design a specific ACT-defective FeFET model, which includes the physical impact of the defect on the electrical parameters of defect-free models, and calibrate the model with measurement data. Fault modeling is performed based on circuit-level simulations, and dedicated test solutions are proposed.
help_outline