Device-Aware Test for Threshold Voltage Shifting in FeFET

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Device-Aware Test for Threshold Voltage Shifting in FeFET

Conference Paper (2025)

Author(s)

Changhao Wang (Chinese Academy of Sciences, Politecnico di Torino)

S. Yuan (TU Delft - Computer Engineering)

N Kolahimahmoud (Politecnico di Torino)

H. Xun (TU Delft - Computer Engineering)

Nicolo Bellarmino (Politecnico di Torino)

Danyang Chen (Shanghai Jiao Tong University)

Chujun Yin (Chinese Academy of Sciences)

M. Taouil (TU Delft - Computer Engineering)

M. Fieback (TU Delft - Computer Engineering)

S. Hamdioui (TU Delft - Computer Engineering)

undefined More Authors (External organisation)

Research Group

Computer Engineering

DOI related publication

https://doi.org/10.1109/ITC58126.2025.00052

Device-aware test Defect modeling Memory test FeFET

To reference this document use:

https://resolver.tudelft.nl/uuid:eac06cdd-7385-4d5c-bc3d-b28b5e9f7c6b

More Info

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Publication Year

2025

Language

English

Research Group

Computer Engineering

Bibliographical Note

Green Open Access added to TU Delft Institutional Repository as part of the Taverne amendment. More information about this copyright law amendment can be found at https://www.openaccess.nl. Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Pages (from-to)

410-413

Publisher

IEEE

ISBN (print)

979-8-3315-7042-2

ISBN (electronic)

979-8-3315-7041-5

Event

2025 IEEE International Test Conference (ITC) (2025-09-20 - 2025-09-26), San Diego, United States

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Abstract

Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) technologies, especially in embedded systems and edge computing. However, due to their physical characteristics, FeFETs exhibit unique defects—such as Threshold Voltage Shifting (TVS) caused by trap charges in the oxide layer—that are not captured by conventional defect models. This study adopts the Device-Aware Test (DAT) methodology to model these defects by incorporating their impact into the electrical parameters, calibrated using measurement data. Defect injection, circuit-level simulations, and fault analysis are performed to derive realistic fault models. Finally, the March algorithm and Design-for-Test (DfT) techniques are proposed to effectively detect these defects.

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