Device-Aware Test for Threshold Voltage Shifting in FeFET
Changhao Wang (Chinese Academy of Sciences, Politecnico di Torino)
S. Yuan (TU Delft - Electrical Engineering, Mathematics and Computer Science)
N Kolahimahmoud (Politecnico di Torino)
H. Xun (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Nicolo Bellarmino (Politecnico di Torino)
Danyang Chen (Shanghai Jiao Tong University)
Chujun Yin (Chinese Academy of Sciences)
M. Taouil (TU Delft - Electrical Engineering, Mathematics and Computer Science)
M. Fieback (TU Delft - Electrical Engineering, Mathematics and Computer Science)
S. Hamdioui (TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) technologies, especially in embedded systems and edge computing. However, due to their physical characteristics, FeFETs exhibit unique defects—such as Threshold Voltage Shifting (TVS) caused by trap charges in the oxide layer—that are not captured by conventional defect models. This study adopts the Device-Aware Test (DAT) methodology to model these defects by incorporating their impact into the electrical parameters, calibrated using measurement data. Defect injection, circuit-level simulations, and fault analysis are performed to derive realistic fault models. Finally, the March algorithm and Design-for-Test (DfT) techniques are proposed to effectively detect these defects.