Device-Aware Test for Ion Depletion Defects in RRAMs

Conference paper (2023)

Authors

H. Xun Computer Engineering - EEMCS
S. Yuan Computer Engineering - EEMCS
M. Fieback Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS , CognitiveIC
S. Hamdioui Computer Engineering - EEMCS , CognitiveIC
Hassen Aziza Aix Marseille Université
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2023 H. Xun, S. Yuan, M. Fieback, M. Taouil, S. Hamdioui, Hassen Aziza
DOI
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https://doi.org/10.1109/ITC51656.2023.00041
Fault modeling RRAM test Device-aware defect model Design-for-Testability (DfT) Linear resistors
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Published Date

2023

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

Many companies are heavily investing in the commercialization of Resistive Random Access Memories (RRAMs). This calls for a comprehensive understanding of manufacturing defects to develop efficient and high-quality test and diagnosis solutions to push high-volume production. This paper identifies and characterizes a new defect based on silicon measurements; the defect is called Ion Depletion (ID). In our case study, 45% cycles suffered from an intermittent reduction in high resistance state and did not impact low resistance state. The paper shows that the traditional fault modeling based on linear resistors as a defect model is not accurate. To address this challenge, the Device-Aware (DA) defect modeling method is applied; an RRAM model of the defective device is developed and calibrated using measurements to accurately describe the impact of the defect on the electrical behavior of the memory device. Afterward, fault analysis is performed based on the DA defect model, and appropriate fault models are introduced; they show that the ID defect may sensitize undefined state faults. Finally, dedicated test and diagnosis solutions for the ID defect are proposed.