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Exploring the use of extreme temperatures to facilitate fault propagation in ReRAMs

Journal Article (2025)
Author(s)

Thiago Copetti (RWTH Aachen University)

A. Chordia (RWTH Aachen University)

M. Fieback (TU Delft - Computer Engineering)

M. Taouil (TU Delft - Computer Engineering)

Said Hamdioui (TU Delft - Computer Engineering)

L. M. Bolzani Poehls (IHP - Leibniz Institute for High Performance Microelectronics)

Research Group
Computer Engineering
DOI related publication
https://doi.org/10.1016/j.microrel.2025.115919
More Info
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Publication Year
2025
Language
English
Research Group
Computer Engineering
Volume number
175
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Abstract

Resistive Random-Access Memories (ReRAMs) represent a promising candidate to complement and/or replace CMOS-based memories adopted in several emerging applications. Despite all their advantages – mainly CMOS process compatibility, zero standby power, and high scalability and density – the use of ReRAMs in real applications depends on guaranteeing their quality after manufacturing. As observed in CMOS-based memories, ReRAMs are also susceptible to manufacturing deviations, including defects and process variations, that can cause faulty behaviors different from those observed in CMOS technology, increasing not only the manufacturing test complexity but also the time required to perform the test. In this context, this paper proposes to study the use of temperature to facilitate fault propagation in ReRAMs, reducing the required test time. A case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library was adopted. During the proposed study, a total of 17 defects were injected in different positions of the ReRAM cell, and their respective faulty behavior was classified into conventional and unique faults, considering three different temperatures (25, 100, and -40 °C). The obtained results show that the temperature can, depending on the position of the defect, facilitate fault propagation, which reduces the time required for performing manufacturing testing.