This dissertation, conducted within the discipline of Electronic Science and Technology (specialization in Microelectronics and Solid-State Electronics), focuses on Resistive Random Access Memory (RRAM), an emerging non-volatile memory technology known for its high density and zero static power consumption. RRAM enables fast write and read operations in the nanosecond range and supports Computation-in-Memory (CIM), making it a strong candidate to replace Flash or even Dynamic Random Access Memory (DRAM). Recognizing its potential, both academic institutions and industry leaders have been actively developing RRAM prototypes, with some already reaching the commercial market. To ensure reliability, high-quality testing is essential for guaranteeing product quality.

This dissertation mainly focuses on developing effective test methodologies and robust designs for RRAMs. We begin by examining the RRAM manufacturing process and identifying potential physical defects at each stage through a comprehensive literature review and silicon measurements. To facilitate in-depth analysis, we develop a complete and systematic RRAM simulation platform, integrating a MATLAB-based simulation controller and fault analysis scripts integrated with a complete RRAM circuit design. The controller automates and manages all simulation procedures, while the circuit design comprises a 1T-1R memory array along with essential peripheral components such as write drivers and sense amplifiers. To achieve fast and accurate electrical simulations, we introduce two compact models for RRAMs. These models are optimized and calibrated using extensive measurement data from RRAM devices. We further calibrate the model with industrial measurements from ST Microelectronics. It enables robust device/circuit co-design, accounting for PVT variations and ensuring the reliability and efficiency of RRAM systems..... ... Read more

The automotive industry is experiencing a significant shift towards advanced electronic and software integration, driven by the increasing demand for self-driving and autonomous vehicles. With electronics now making up a major portion of vehicle costs, ensuring their reliable operation is critical. However, as the complexity of automotive systems increases, so do the risks associated with malfunctions, requiring a critical need for robust safety measures. Functional Safety (FuSa), as defined by ISO 26262, provides a framework for addressing these concerns at different stages of the safety lifecycle. The primary aim of FuSa is to develop Safety Mechanisms (SM) to detect faults and recover from them. The efficiency of these SMs is indicated by Diagnostic Coverage (DC), which represents the percentage of detected faults. In this context, there are several challenges in verifying the functional safety of automotive chips, especially with RTL designs. For example, identification of safe faults is one of the initial steps in FuSa verification. Discrepancies are observed in their classification when utilising different techniques such as Automatic Test Pattern Generation (ATPG), formal methods and fault injection simulation. This raises questions about the accuracy of overall results obtained from these tools as well. Varying outcomes from fault simulation EDA tools in classifying faults may result in different Automotive Safety Integrity Levels (ASIL) assigned to the component being assessed. This discrepancy would misrepresent the component's ability to reduce associated risks, highlighting the importance of conducting a detailed analysis and comparison of the tools.

The thesis provides a comprehensive evaluation of EDA tools utilized for Functional Safety Verification, focusing on RTL designs. Scripts are developed to automate fault simulation flows of two prominent FuSa EDA tools, XFS by Cadence and VC Z01X by Synopsys, and derive automatic comparisons. By comparing these tools, their strengths and limitations are analyzed. XFS exhibits limitations in fault propagation on input and output ports, resulting in the omission of certain fault scenarios. VC Z01X showcases faster fault simulation capabilities along with an extensive feature set for fault simulation, but lacks support for transient fault injection on a section of the fault subspace. By applying the automated tool flows on a FIFO design enabled with ECC, the DC obtained from XFS and VC Z01X are 68.96% and 80.47% respectively, showcasing a major difference. These findings highlight the importance of a holistic verification methodology that accurately estimates diagnostic coverage.

A novel verification methodology is proposed, which combines the strengths of XFS and VC Z01X to optimize the efficiency and accuracy of fault simulation. Leveraging VC Z01X's concurrent engine for parallel fault injection and XFS's capabilities to cover the unexplored fault space, this integrated approach provides comprehensive fault coverage. The flow also provides users the capability to update fault classification results based on manual analysis or designer inputs, thereby changing the DC as well. The verification methodology is applied to the AutoSoC benchmark suite, an automotive System-on-Chip with configurable SMs. Based on the results, additional SMs are implemented in the AutoSoC design - duplication of pipeline stages with temporal redundancy and ECC on internal memories. This leads to an estimated area increase of 1.4x as compared to the baseline design, but also results in the qualification of an ASIL C level component with a DC of 97.79%. The baseline verification flow included in the benchmark suite provides a DC of 98.36%, which is an over estimation of the actual coverage. The proposed methodology provides a more accurate coverage by taking into account the maximum possible fault space and considering transient faults as well. While there remains room for further improvement in verification methodologies, this framework effectively addresses the fault space required for FuSa verification and provides an accurate estimation of Diagnostic Coverage. ... Read more

The increasing complexity of Integrated Circuits (ICs) and stringent quality requirements in industries like automotive have contributed to increasing test development time. Virtual testing methodologies, such as AMS-VT, can be used for pre-silicon debugging of test programs, optimizing the test development process. However, AMS-VT has shown limitations in their usage due to the absence of accurate loadboard models, especially in capturing site-to-site variations. To address the lack of an accurate loadboard model for pre-silicon debugging, this research proposes a framework for generating an accurate loadboard model by integrating parasitic effects and possible reflections under real-world conditions.

The proposed framework consists of three main stages. The first stage is an automated netlist generation phase, during which an ideal single-site netlist is created from a multisite loadboard schematic. The ideal netlist is generated considering the AMS-VT environment so that it can be seamlessly integrated into the current virtual testing environment. In the next stage, Cadence PowerSI, which is an Electronic design automation (EDA) tool for parasitic extraction, is automated to extract the parasitics (R, L, G, and C) for all the channels included in the ideal netlist. Finally, in the last stage, a methodology is developed to integrate the parasitics and reflection due to impedance mismatch in the ideal netlist. To improve the accuracy, a static model of the relay was developed that considers its characteristics, such as on-state resistance and off-state current leakage. All these stages are then automated and combined to create a framework that can effectively generate an accurate loadboard netlist that predicts site-to-site variations.

The framework is then validated, with each stage verified independently. The generated ideal single-site netlist was verified against a golden simulation. This verification displayed that the functionality of the generated netlist was accurate and could integrate with AMS-VT seamlessly. The parasitics extracted from PowerSI were validated using a test Printed Circuit Board (PCB) with multiple configurations. This showed that the simulation results using extracted parasitics were within 1% error compared to the IR drop analysis. The relay model was also validated by comparing it with its datasheet, proving that the model accurately considered the physical characteristics. The third stage was then validated by comparing it with PSpice simulations, demonstrating that the model's results were accurate, with the maximum error being below 1.6% for multiple voltages and frequencies. The complete framework was then validated against a physical loadboard, showing maximum errors of less than 2% across all sites and improved timing accuracy for pulse width, reducing it to 0.41% for the proposed framework from 1.6% for the previous methodology. This validation proved that the loadboard generated by the framework accurately modelled parasitics and reflections. The model also accurately accounted for temperature variations, demonstrating its effectiveness in changing operating conditions. By introducing this framework to generate an accurate loadboard model, this research enables a virtual testing environment for faster and more reliable test development, reducing the time-to-market for semiconductor products.
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Resistive random access memory (RRAM) is an emerging memory technology that has the potential to replace dynamic random access memory (DRAM) or FLASH. The current memory technology suffer from scalability issues. RRAM can be used as potential replacement for Flash and DRAM. RRAM stores information using resistance states instead of charge. RRAM is non-volatile memory, power efficient, scalable and compatible with the current CMOS process.
Before RRAM can be commercialized the quality of RRAM devices needs to be guaranteed. For this we need to diagnose RRAM devices. The diagnosis allows us to improve the manufacturing process as well as built defect models for memory testing. The traditional fault models do not incorporate the non-linear behaviour of the RRAM device. As a result, tests are created for the wrong test space resulting in a lower yield and more test escapes. To increase the yield and create more reliable fault models, defect models that incorporate the physical defect of the RRAM device are required. To ensure the manufacturing quality of the RRAM devices and for memory testing of RRAM the characterization and diagnosis of RRAM is required. The electrical characterization of RRAM is cheap, fast and is used to evaluate the performance of RRAM. For diagnosis electrical characterization has not been used before.
This work uses the electrical characterization of RRAM to automatically identify defective RRAM devices which can be used for diagnosis. For the defect identification, the key parameters are determined. To assess the performance of the defect identification algorithms the RRAM devices are labelled manually. In total five methods have been implemented to automatically label defective RRAM devices. A statistical analysis is performed on the RRAM devices. Using the labelled data the devices are compared to a nominal device to identify defects in RRAM. Furthermore, K-means, KNN and a CNN algorithm is applied to RRAM. The classification algorithms allow the automatic identification of defective RRAM devices which can be used for diagnosis.
The metrics used for the statistical analysis are insufficient to accurately identify defective RRAM devices. The nominal device method classifies 81% of the device correctly using the euclidean algorithm. The best performance is obtained for the supervised learning algorithm. K-NN classifies 94% of the cycles correct and 84% of the devices. If the data is not labelled the unsupervised learning algorithm can be used. Kmeans classifies 79.6% of the devices correctly which is slightly worse than K-NN. The CNN classifies 67% of the devices correctly using 20 epochs. However, the CNN has not yet been optimized and needs to be improved. For unlabelled data, the unsupervised learning algorithm should be used and for labelled data the K-NN. The electrical characterization of RRAM devices using machine learning looks promising and is much cheaper compared to optical characterization and memory tests. If in the future the defective devices can be linked to the underlying defect, this will lead to cheaper diagnosis of RRAM devices and allow the creation of accurate fault models.

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Resistive Random-Access Memory (RRAM) is an emerging memory technology that has the possibility to compete with mainstream memory technologies such as Dynamic Random-Access Memory (DRAM) and flash memory. The reason why RRAM has not seen mass adoption yet is due to its defect-prone nature. The resistance of RRAM can assume any value within its operating range and its resistance can be divided into five states instead of the regular two logic states. Conventional test techniques are incapable of detecting unique faults due to their inability to distinguish between all five cell states, resulting in a large number of test escapes. Therefore, new test methods, such as Design-For-Testability (DFT), need to be developed to reduce the number of test escapes and ensure customer satisfaction. This work proposes two new DFTs: Parallel-Reference Read (PRR) and Closed-Loop Write (CLW). The PRR DFT is a replacement for the regular read circuit, which enables the detection of all five cell states, while the CLW DFT is an addition to the regular write circuit, which introduces feedback during the write operation. From these two DFTs, the PRR DFT is selected for further development and its design is validated. From the validation, it is concluded that the PRR DFT can detect all five cell states. Moreover, under process variations, the PRR DFT will provide the correct output in 95.90% of the cases. Furthermore, the PRR DFT improves the overall resistive-defect detection capability by 14.79% when compared to a regular read circuit. Finally, the PRR DFT offers 100% identified fault coverage while only requiring 4N write operations, 5N read operations and an area overhead of 14N_c transistors, where N and N_c are the total number of cells and the total number of columns in the RRAM array, respectively. ... Read more

Resistive RAM, or RRAM, is one of the emerging non-volatile memory (NVM) technologies, which could be used in the near future to fill the gap in the memory hierarchy between dynamic RAM (DRAM) and Flash, or even completely replace Flash. RRAM operates faster than Flash, but is still non-volatile, which enables it to be used in a dense 3D NVM array. It is also a suitable candidate for computation-in-memory, neuromorphic computing and reconfigurable computing. However, the show stopping problem of RRAM is that it suffers from unique defects, which is the reason why RRAM is still not widely commercially adopted. These defects differ from those that appear in CMOS technology, due to the arbitrary nature of the forming process. They can not be detected by conventional tests and cause defective devices to go unnoticed. Therefore, new tests need to be developed that properly include the physics of a defective device in a RRAM model. Device-aware testing (DAT) is the state-of-the-art solution to this problem. By accounting for the unique physics of an RRAM device, DAT is able to detect unique RRAM defects. However, DAT bases its results on relatively compact electrical models, which do not account for randomness present in e.g. the forming of the filament and local temperature fluctuations. Meanwhile, many low-level physical models exist already that can model this randomness and provide accurate insights into the physical specifics of RRAM. These models do, however, hardly ever analyze the effects of defects. The contribution of this work is to expand and improve one of the state-of-the-art physical models to analyse manufacturing defects on a low, near atomic-level scale. For the first time, the characteristics of a defect can be described in the physical shape of the defect, rather than only the electrical consequences of a black box device. This enables deep level analysis and characterization of defects, the results of which improves DAT to detect even more unique defects. The model is applied to four types of RRAM-related defects: oxygen vacancy density fluctuation, oxide thickness variation, electrode roughness, and contamination by impurities. The effect of the defects on the conductivity of the device are observed and explained, and their unique non-linear behavior is confirmed by simulation. Dynamic defects are not yet included, but the model does provide an extensive static characterization of unique RRAM defects, providing insights into their behavior and improving the quality of DAT. Finally, a discussion is presented which criticizes the reproducability of the referenced defect-free model, but also shows the potential of this work's model to be improved. ... Read more

Many alternative computer architectures that use emerging devices are under investigation to address the challenges current architectures and technologies face. Computation-in-memory (CIM) architectures are one among these alternative that tries to solve these challenges by performing computations in the memory structure as opposed to transferring the data to a central processing unit.One class of these CIM architectures employs memristive devices. These are non-volatile devices that store data as a resistance, and are highly compatible with traditional CMOS process. Many research centers and companies are prototyping such architectures. Efficient and high-quality test solutions are required for these architectures, which is the subject of this thesis. This thesis presents a methodology for testing any CIM architecture, focusing on their memory and computation configurations, and applies this methodology to an existing CIM architecture as an example. The configurations are tested in the mentioned order for maximum fault coverage, while minimizing test development complexity. The testing method is structural rather than functional, thereby maximizing and guaranteeing fault coverage. To create accurate tests, device-aware testing is employed to model these defective devices. As a case study, the methodology is applied to scouting logic, a bit-wise logic CIM architecture that performs operations on data stored in memristors. Defects in the memory array as well as in the peripheral circuitry were injected and simulated to obtain realistic faults. The resultant fault analysis shows that there exist faults that are unique to the computation configuration and are not observed in the memory configuration. This implies that testing a CIM architecture only as a memory will lead to test escapes. Hence, the proposed test solution tests both the memory and computation configuration, and detects all faults. ... Read more