Many alternative computer architectures that use emerging devices are under investigation to address the challenges current architectures and technologies face. Computation-in-memory (CIM) architectures are one among these alternative that tries to solve these challenges by performing computations in the memory structure as opposed to transferring the data to a central processing unit.One class of these CIM architectures employs memristive devices. These are non-volatile devices that store data as a resistance, and are highly compatible with traditional CMOS process. Many research centers and companies are prototyping such architectures. Efficient and high-quality test solutions are required for these architectures, which is the subject of this thesis. This thesis presents a methodology for testing any CIM architecture, focusing on their memory and computation configurations, and applies this methodology to an existing CIM architecture as an example. The configurations are tested in the mentioned order for maximum fault coverage, while minimizing test development complexity. The testing method is structural rather than functional, thereby maximizing and guaranteeing fault coverage. To create accurate tests, device-aware testing is employed to model these defective devices. As a case study, the methodology is applied to scouting logic, a bit-wise logic CIM architecture that performs operations on data stored in memristors. Defects in the memory array as well as in the peripheral circuitry were injected and simulated to obtain realistic faults. The resultant fault analysis shows that there exist faults that are unique to the computation configuration and are not observed in the memory configuration. This implies that testing a CIM architecture only as a memory will lead to test escapes. Hence, the proposed test solution tests both the memory and computation configuration, and detects all faults.