The urgency for high-security products for industrial networks is increasing as malicious hackers are improving their accessibility tools. A common practice for a company to protect its sensitive data is network segmentation. The network is segmented in different domains with distinctive security levels. The sensitive data is stored and managed within the domain of the highest security level. To access this domain from another domain of a lower security level, a highly reliable connection is required. You want to have full control over the incoming and outgoing data flow between these network segments. A variety of solutions provide a highly-secured connection to link those segments which differ in range of features and control. An upcoming trend is the network diode. This device will allow data flow in only one direction. All the flows going into the opposite direction are being blocked. However, to feature an arbitrary flow between two network segments, the diode should consist of a numerous amount of properties. To narrow down the optional features a network diode should provide, this thesis will focus on TCP streams. TCP is one of the most common protocols used in internet traffic. Furthermore, TCP is a challenging protocol as it is a connection-oriented bidirectional protocol, which is intrinsic controversial with the concept of the data diode. To ensure the security of the data diode, this thesis will focus on a complete hardware design of the data diode. Software inside the data diode is still a risk for a security breach. This thesis will investigate the critical operations of TCP to implement them in the data diode. The aim is to utilise TCP's characteristic operations of the acknowledgement managing, the sliding window system, the congestion control algorithm, and explores the advantage of existing TCP options. To evaluate the feasibility of a high performance data diode featuring TCP, the system is broken down to project the behaviour of a TCP stream on a one-way connection device. This results in two separate TCP connections, with only the precious data as common shared information. This model requires a buffer at one side of the diode to transmit data in a TCP stream. To analyse and examine the influence of the diode configuration to the size of the buffer, a diode module is created to simulate in a OMNeT++ environment. From this simulation tool, a minimal set of parameters can be extracted that are essential to configure the data diode. With the assumption of having control on the network management at the trusted side of the diode, a configuration without a congestion control algorithm and without adding radical TCP options is recommended to minimise the required buffer size. Thereafter, this thesis proposes a high-level hardware design to implement the data diode on a hardware project. The design focuses on the high data rate which should be available to satisfy the data diode's requirements. Finally, this thesis concludes with an elaboration on the assumptions of the limitations of the network environments and recommends features to implement in future work.

Traditional Artificial Neural Networks(ANNs)like CNNs have shown tremendous opportunities in various domains like autonomous cars, disease diagnosis, etc. Proven learning algorithms like backpropagation help ANNs in achieving higher accuracy. But there is a serious challenge with the increasing popularity of traditional ANNs is of energy consumption and computational complexity. Spiking Neural Networks (SNNs) are considered to be next-generation neural networks that are capable of doing complex deep learning applications at fraction of energy that is needed in current deep learning applications because of its similarity to biological neurons. However, SNN is still not able to match the classification accuracy of ANNs which poses a big challenge for wide acceptance of SNN in various applications as traditional learning methods like backpropagation are not possible in SNN. During training of a neural network the weight matrix is of the highest importance as it eventually decides the trajectory of learning. Currently, one existing solution is to just manually convert ANNs into SNNs to get weight matrix which doesn't focus on getting weight matrix from a small dataset and doesn't consider spiking neuron parameters. We propose a novel N-shot training methodology that is capable of providing a weight matrix for SNN and can give sufficient classification accuracy. The methodology not only provides the weight matrix but can perform training with a very small dataset(up to 1 image per class) and still obtain considerably higher accuracy. For a reduced MNIST dataset, the method can give an accuracy of 71.68% 10 images per class.

This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed inter-chip communication. The interface is composed of LVDS transceivers as external I/O buffers, and an all-digital data recovery, which can calibrate the received data phase to be aligned to the 90◦ phase of the received half-rate reference clock, for error free data sampling. The proposed data recovery adopts a full-digital scheme, which uses time-to-digital converters (TDC) as phase acquisition, a digitally-controlled delay line (DCDL) to calibrate the phase, and a finite-state machine (FSM) as the control unit. Reference clock generated from phase-locked loops (PLL) or delay-locked loops (DLL) is not needed for the proposed data recovery. The interface is implemented in UMC 65 nm Low-leakage technology, with circuits designed at both transistor-level and RTL-level. The post-layout simulation shows the proposed interface works properly with data rates from 412.4Mbps to 1.25Gbps in all process corners. The total layout area is 688 x 87 µm, and the total power consumption is 16.74 mW. 

The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC. A fully automatic scripted flow is described, constructing an optimized, error-free ASIC. The design area is limited to 3.5 um², to allow it to be manufactured with the cheapest 65 nm prototyping run available at IMEC. In order to achieve this small design area, a new 24-port register file design has to be devised. In its current state, it is implemented using standard logic cells. Clever optimizations involving cell padding and minimum overhead power routing are necessary to reduce a total routing overcongestion from 7% to zero. This implementation is expected achieve a clock speed of 141 MHz, only limited by the ρ-VEX reconfiguration logic. By lowering the frequency to 100 MHz, the energy dissipation is reduced by 96%, to a total of 367 uW/MHz. This is comparable to similar VLIW designs. Using LVDS communication clocked at four times the core frequency, a data bandwidth of 4 Gbit/s is achieved using only 26 external pins. This allows the main data and instruction memory to reside off-chip. To ensure a correct design, it is verified using DRC, LVS, and ERC. For improved reliability, IR-drop is kept within 1% of the core voltage, using minimal power routing. Furthermore, the effect of electromigration is kept extremely low such that the mean time to failure on nets is 90 years. The scripted flow will aid in prototyping, allowing accurate estimates to be calculated in a mere 7% of the original time. Proposals for a future design are expected to reduce the register file area and power dissipation by more than 40%. By improving the pipeline and shortening the critical path, a two to four fold improvement in clock speed can be expected, without adversely affecting power dissipation.

Some server hosters facilitate cyber crime either intentionally (so called “bulletproof hosters”) or unintentionally (“bad hosters”). When dealing with uncooperative hosters during forensic investigations, it may sometimes be necessary to collect data or information on the servers without help from the owner of the server. Data within the RAM might prove insightful in, for example, determining active processes or reveal crypto graphically interesting information like encryption keys. The thesis explains key concepts within memory organization and the PCIe standard.Afterwards, it discusses several techniques for RAM acquisition and categorizes and evaluates them using a model-based approach. The thesis then dives deeper into DMA-based memory acquisition using PCIe and proposes several improvements to current DMA attacks in order to create a better memory acquisition technique. A novel memory acquisition technique is created by hot-plugging aPCIe device and skipping over the regular enumeration procedure. This techniqueal lows the memory acquisition to be executed without a reboot and provides a stealth approach to accessing the memory.  

Conversion from digital information to spike trains is needed for Spiking Neural Networks. Moreover, it is one of the most important steps for Spiking Neural Networks. This conversion could lead to much information loss depending on which encoding algorithm is used. Another major problem that can occur in a specific use-case is the limited bandwidth for the spikes that get generated through the encoding algorithm. In this thesis, we propose population Step Forward Encoding algorithm. This algorithm takes the signal encoding accuracy of Step Forward encoding algorithm and makes it into a population, generating multiple spike trains. This allows a higher threshold to encode a large part of the signal, increasing the efficiency. We show that population Step Forward Encoding algorithm doesn't just work good for the signal encoding accuracy, but also for the classification accuracy. Moreover, population Step Forward Encoding algorithm does not only have a high efficiency with a low spike count, it can also achieve higher efficiency with higher spike count. Thus, population Step Forward can make most use of a limited bandwidth of spikes.

Neuromorphic electronic systems have used asynchronous logic combined with continuous-time analog circuits to emulate neurons, synapses, and learning algorithms. It is attractive because of its low power consumption and feasible implementation. Typically, the neuron firing rates are lower than the modern digital systems. Thus, the endpoints of neuromorphic electronic systems are clusters of neurons instead of individual neurons. Address event representation (AER) was proposed in 1991 to multiplex communication for a cluster of neurons into an individual communication channel. AER circuits provide multiplexing/demultiplexing functionality for spikes that are asynchronously generated by/delivered to an array of individual neurons. Asynchronous techniques are not only used in neuromorphic electronic systems, but also widely used in globally asynchronous and locally synchronous (GALS) SoCs, or SoCs with full-asynchronous solutions. However, commercial tools on the market do not support designing asynchronous circuits, making the circuits cannot be adopted easily by most products. This thesis aims at addressing the challenge by providing an asynchronous library establishment strategy. The strategy uses SR-latches as standard asynchronous cells together with logic gates to build an AER communication circuit. With the strategy, the performance of using a modified traditional arbiter in the AER transmitter can be compared favourably with using state-of-the-art arbiters. A back-end flow and a verification flow are developed to evaluate the performance of the design as well as to check the feasibility of the strategy. The proposed 32-bit AER transmitter under TSMC 28nm CMOS technology sacrifices area and power to achieve better timing performance, where the modified arbiter inside has an 11.54% better response time than the arbiter who used to be the best in an old comparison.

DTB Multiplexer is a component within an NXP chip called the BAP3. This component provides a testing functionality for the chip. This component is purely combinational, and requires no clock, however this makes the component wiring-costly. This high wiring requirement leads to the area constraint imposed by the wiring demand rather than cell area, and this also leads to the DTB multiplexer reducing the placement area available for other modules. In this thesis, the wiring area is going to be estimated as the amount of congestion, which would cause detour in the design which results in extra wiring. In this thesis, DTB multiplexer is placed by external method instead of using the place and route tools usually used by the design team. Instead, the placement is done on MATLAB which is later ported to the place and route tools using script. The placement algorithm implemented in MATLAB is primarily based on two algorithm, Dplace for initial preplacement, which in turn utilizes diffusion preplacement algorithm, and modified C-ECOP for the congestion reduction. More detailed congestion estimation done by using an additional routing estimation algorithm which is based on One-Steiner routing algorithm. The result indicates that the modified C-ECOP can be used to reduce congestion, thus wiring area when paired with a good initial placement algorithm, but the initial placement algorithm and detailed congestion estimation algorithm with one-steiner could be further improved, and further work is needed to integrate the result with commercial

Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. This provides a higher-level method for defining interfaces between components as opposed to existing bit- and byte-based interface specifications. In this thesis, an open-source intermediate representation (IR) is introduced which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi’s streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system. The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior. To demonstrate this IR, a grammar, parser, and query system have been created, and paired with a backend targeting VHDL.

In the recent past, real-time video processing using state-of-the-art deep neural networks (DNN) has achieved human-like accuracy but at the cost of high energy consumption, making them infeasible for edge device deployment. The energy consumed by running DNNs on hardware accelerators is dominated by the number of memory read/writes and multiplyaccumulate (MAC) operations required. As a potential solution, this work explores the role of activation sparsity in efficient DNN inference. As the predominant operation in DNNs is matrix-vector multiplication of weights with activations, skipping operations and memory fetches where (at least) one of them is zero can make inference more energy efficient. Although spatial sparsification of activations is researched extensively, introducing and exploiting temporal sparsity is much less explored in DNN literature. This work presents a new DNN layer (called temporal delta layer) whose primary objective is to induce temporal activation sparsity during training. The temporal delta layer promotes activation sparsity by performing delta operation facilitated by activation quantization and l1 norm based penalty to the cost function. During inference, the resulting model acts as a conventional quantized DNN with high temporal activation sparsity. The new layer was incorporated as a part of the standard ResNet50 architecture to be trained and tested on the popular human action recognition dataset (UCF101). The method caused 2x improvement in activation sparsity, with 5% accuracy loss.

An increasing amount of critical applications use DRAM as main memory in its computing systems. It it therefore extremely important that these memories function correctly during their lifetime in order to prevent catastrophic failures. Already during the design phase, the reliability of the circuit needs to be predicted so that a reasonable lifetime expectation can be given. Although the importance of reliability analysis is clear, in literature not much research on DRAM reliability is available to designers. This thesis proposes a two phased DRAM reliability prediction model that can be used in the circuit design phase. During the first phase, the circuit performance is analyzed for different wear-out mechanisms affecting different subcomponents in the design. In the second phase, the results of the first phase are then used to determine the reliability of the circuit. In the first phase, the wear-out effects of Bias Temperature Instability (BTI) Hot Carrier Injection (HCI) and radiation trapping as well as transistor mismatch are examined. BTI is modeled using the RD-model, HCI with the lucky electron model, transistor mismatch with Pelgrom’s model. Wear-out caused by radiation trapping is modeled as Gate Induced Drain Leakage (GIDL), the data for which are derived from retention time degradation measurements of an irradiated commercial DRAM. The circuit performance is analyzed per subcomponent of the DRAM design in a range of different metrics. Furthermore, the aging effects on a dwonscaled version of the circuit are investigated. In the second phase, reliability functions are derived from the results from phase one per wear-out mechanism and per subcomponent. These reliability functions are used in an analytical reliability model which yields the overall circuit reliability. The results from the first phase show degradation of the retention time as well as degradation of sensing delay metrics. Due to the relative low duty factor of memory cells, BTI and HCI have minor impact on the memory cell circuit performance. Radiation however, renders the circuit useless once the Total Ionizing Dose (TID) becomes more than 126 krad. On other subcomponents than the memory cells, BTI and HCI shift the reference voltage which results in an increase of retention time. BTI and HCI stressing of the sense amplifier also slightly increases retention time but mainly increases sensing delay. For both reference cells and the sense amplifier it holds that higher radiation doses break down the circuit completely. The same effects hold for the downscaled circuit, although the observed effects are more severe than in the unscaled device. The system reliability prediction in the second phase shows the importance of individual reliability prediction of the subcircuits and wear-out mechanisms. Via the individual analysis, it becomes clear that the system reliability is mostly impacted by the degradation of the sense amplifier delay due to BTI and HCI. Other metric variations, like the increase in retention time caused by the reference cells, have less impact. It was found that the system reliability decreases to 0.84 after 1·108s at a stressing temperature of 300K.

Neurons in Spiking Neural Networks (SNNs) communicate through spikes, similarly that neurons in the brain communicate, thus mimicking the brain. The working of SNNs is temporally based, as the spikes are time-dependent. SNNs have the benefit to perform continual classification, and are inherently more low-power than other Artificial Neural Networks (ANNs). Both the SNNs and other ANNs need to be trained to perform specific tasks. There are several types of methodologies to train SNNs, but there is yet no silver bullet. Backpropagation algorithms can train other ANNs, but SNNs cannot be trained using this algorithm since the spikes are not differentiable. Methods like Spike Timing Dependent Plasticity (STDP) or Liquid State Machine (LSM) have their limits. Where the complexity of SNNs depends on the dataset, the number of neurons, and other factors. There were currently no known SNN implementations for the given gesture, achieving near state-of-the-art results. The problem with the dataset is that usually no gesture is performed in front of the . The datasets contain noise, and some data samples belong to two or more classes simultaneously. The objective of this work is to develop an architecture and training methodology, that allows the classification of the dataset using SNNs. This work presents a novel, architectural training methodology Suino, which addresses the above problems. The architecture consists of two components: the first is the spatial classifier, and the second component is the temporal classifier. The frames from the dataset are filtered in the first stage, i.e. the spatial classifier. The output of the spatial classifier is the input for the temporal classifier, which deals with the temporal properties of the data. Suino does not provide false positives, that is the neurons do not spike on the input dataset if the input dataset does not belong to any of the trained classes; hence the method is robust. The training method is built around these components, existing of different classical training methods: backpropagation, clustering, or any other consisting of fixed threshold method for auto label correction. The second stage consists of a temporal classification method, trained using the Tempotron learning rule. The time-series dataset of gestures validated Suino. On the test set, the baseline method had an accuracy of 97.0% with 35K parameters, while the presented method had an accuracy of 90.87% with 21K parameters. Hence, the method is more robust against false detections and continuously performs classification.

Forensics is the art of gathering evidence, which for electronics amounts to accurately recovering data. Often, this can only be archived with state-of-the-art hacking techniques. However, replicating state-of-the-art research in hardware security can be difficult, due to the large number of components and connections. To counter this, a custom Printed Circuit Board (PCB) is presented, that aids with hardware attacks, and allows them to be executed in a reliable and reproducible way. The PCB is targeted specifically towards hardware encrypted USB drives, and provides accessible ways to break out and interact with the target’s electrical components. In the first part of this thesis, the design and fabrication of the platform, called LUPIn, short for Lawful Unlocking of PIN-protected USB drives, is established. The design integrates commonly-used components and functions, making it suitable for a wide range of different attacks and devices. It also incorporates robust and traceable connections to the target. In the second part, LUPIn is verified by implementing it in a real attack. The target is a PIN-protected USB drive, which contains an IC performing key derivation. Since the debug port is not fully secured, a technique called Cold-Boot Stepping is used. This method is specifically designed to circumvent partially disabled debug ports. To analyse the gathered data, it first must be filtered. This filtering is done using a graph-based algorithm. In one crytographic function, an input parameter is used twice with different XOR masks. By analyzing all the filtered data, it is possible to find masked values, and use those to recover the original input value. Concluding, a hardware tooling PCB (LUPIn) is successfully designed, assembled and tested. It proves to be a reliable platform for performing hardware attacks against encrypted USB drives. It makes development of hardware attacks simpler and less time-consuming. In the validation of LUPIN, a real-life USB drive is successfully attacked. Thousands of RAM snapshots are collected and an algorithm is developed to filter this data. A single variable can be extracted, but it ultimately proved insufficient to fully crack the target.

A Spiking neural network (SNN) is a type of artificial neural network which encodes information using spike timing, network structure, and synaptic weights to emulate the information processing function of the human brain. Within an SNN, it is always required to support the spike transmission that travels between neurons(array). This thesis aims to design a customized high-speed interconnect system which supports multi-point communication in a neuromorphic computing system. The burst-mode two-wire protocol in point-to-point communication is applied in this interconnect system, which is designed in high-level modelling with SystemC. In order to improve the utilization of hardware resources, a virtual channel system is involved. Furthermore, this system could be extended to a variable number of neuron arrays to support different types of spiking neural networks. Also, optimization methods are adopted to increase the transmission rate of the system and save unnecessary energy consumption. The interconnect system could achieve a throughput of 3.802 Gbits/s with the given MNIST use case, based on the evaluation of simulation results.

To support the spike propagates between neurons, neuromorphic computing systems always require a high-speed communication link. Meanwhile, spiking neural networks are event-driven so that the communication links normally exclude the clock signal and related blocks. This thesis aims to develop a self-timed off-chip interconnect system with ring topology that supports multi-point communication in neuromorphic computing systems. This interconnect system is implemented in high-level modeling with SystemC and involves the burst-mode two-wire protocol in point-to-point communication. In order to ensure the flexibility of the system, the distributed control system is involved. Further, the system can be configured with different numbers of chiplets to fulfill various spiking neural network structures. We also explore optimization methods, which is a bi-directional ring topology achieving the growth of throughput. Based on evaluation and simulation results, the interconnect system can achieve 4.302Gbps with the specific application scenario.

Spiking Neural Networks(SNN) have been widely leveraged by neuromorphic systems due to their ability to closely mimic biological neural behavior, where information is exchanged and received between neurons in the form of sparse events(spikes). Such neuromorphic systems are highly energy-efficient because the use of a global clock can be avoided by asynchronous event-driven operations. Neurons, as the basic processing units of neuromorphic systems, are required to be low-power and high-speed for the implementation of complex networks. In this work, two fully event-driven digital Integrate-and-Fire(IF) neuron design is presented. Both design exploits the hierarchical structure, which allows the synaptic weights can be accumulated by local compute units in parallel. Instead of using handshake protocols, the proposed design generates on-demand event pulses to drive the weight accumulation, so we call it self-timed. Both neurons are designed by SystemVerilog and synthesized in TSMC 28nm technology. According to the synthesis results, both designs can finish the accumulation of 1024 6-bit weights within 100ns, with a power consumption of 0.055pJ per spike and 0.23pJ per spike respectively.

Spiking neural networks (SNN), as the third-generation artificial neural network, has a similar potential pulse triggering mechanism to the biological neuron. This mechanism enables the spiking neural network to increase computing power compared to the traditional artificial neural network to process complex information. However, a large number of interconnection resources is required. This requirement is highly consistent with the characteristics of the network on chip (NoC). This thesis is aimed at developing a scalable cycle-accurate simulator based on Noxim, which provides a configurable NoC that can simulate neuron-to-neuron communication for delivering spiking traffic. This simulator achieves several configurable metrics including topology and routing schemes, network size, the number of channels, and neuron mapping methods. This thesis then evaluates the effects of these metrics on performance for two kinds of traffic patterns. To take power consumption and area into account, this thesis also provides an approximate estimate of area and power consumption for trade-offs in the early-design stage.