This report details the design of an instrumentation system to be used on a skeleton sled. The system will measure several quantities on a skeleton track for the athlete to learn from. This data is stored during the run using several sensors on the sled and processed and visualised immediately afterwards on a mobile device. The project is tailor-made for skeleton athlete Akwasi Frimpong: he requested a way to get some insight in his steering using his knees and shoulders and its results on his achievements. This thesis focuses on the data processing, communication and visualisation of the data and the software integration of all sensors. The communication is done using Wi-Fi and the visualisation is realised with a web page. The whole system is implemented with an ESP32 microprocessor which functions as a Wi-Fi access point and web server for the user interface.

In September 2018, the Smart Teddy project was founded by a group of researchers within the Hague University of Applied Sciences1 in the Netherlands. The Smart Teddy project is a multidisciplinary project aiming to create an interactive system, using a teddy bear as a focus point, which collects the data needed in order to enable seniors with dementia to live independently for a longer period of time. Over the last three years, three prototypes of the Smart Teddy have been developed. The Smart Teddy project was introduced as a final project for students following the BSc program Electrical Engineering at the Delft University of Technology. Starting in April 2021, a team of six students attempted to further develop the Smart Teddy over the course of 11 weeks. This thesis contains the Human Interaction & Integration subdomain of the Smart Teddy thesis project, where Human Interaction refers to the aspects of the Teddy that encourage interaction with the user, and Integration refers to the combination of all subdomains into one fully functioning prototype. In this thesis, the design choices, implementation methods and verification are discussed. The contribution to the prototype regarding Human Interaction & Integration are the addition of a movement system using pneumatics, the implementation of a flexible touch sensor, the ability for the Teddy to produce audio, to communicate wirelessly with the Base Station, and for all components in the Teddy to communicate with the main controller. The final prototype has been implemented using the Raspberry Pi Pico microcontroller, which was mounted on a custom PCB. All controls are provided by the Pico, and uses I2C, SPI, UART, and analog and digital inputs to communicate with the sensors and actuators. These sensors and actuators were implemented using off-the-shelf breakout boards and drivers, to allow for fast design and test iterations. The movement of the Teddy has been implemented using air pumps and molded silicon rubber, and the tail wagging is implemented using the same principle used for soft robotic grippers. The final prototype is fully functional and meets 16 of the 20 requirements - the requirement concerning speech recognition and the noise produced by the pumps have not been met.

The increasing volume and latency requirements of big data impose challenges on the processing capacity of existing computing systems. FPGA accelerators can be leveraged to overcome these challenges, but questions remain as to how these accelerators are best deployed to accelerate big data frameworks. This work investigates how future big data frameworks should be designed such that they facilitate transparent and efficient integration with FPGA accelerators in the context of SQL workloads. Three big data frameworks are accelerated to answer this question. These implementations offload the evaluation of a regular expression filter to Tidre, an FPGA-based regular expression matcher. First, Dremio is accelerated to obtain a 1750x speedup of the filter operator. Second, Dask is accelerated and a speedup of 92x is achieved for the same operator. Lastly, an accelerated version of Dask distributed is implemented. This implementation is deployed in a cluster environment to attain an end-to-end speedup of 3.6x as well as a reduction of the total cost per query by 23%. It is identified that query exploration phases could be used to increase the impact of existing FPGA kernels. In addition, it is found that the batch size of batch-processing frameworks has a significant impact on the performance of FPGA accelerated big data frameworks in distributed setups. Tuning this batch size can increase end-to-end query throughput up to 2.1x. Finally, future big data frameworks should make use of hardware-friendly and language-independent in-memory formats such as Apache Arrow. Correct alignment of the memory buffers of this data format can further increase the throughput of the system by 2.5x.

Traditional Artificial Neural Networks(ANNs)like CNNs have shown tremendous opportunities in various domains like autonomous cars, disease diagnosis, etc. Proven learning algorithms like backpropagation help ANNs in achieving higher accuracy. But there is a serious challenge with the increasing popularity of traditional ANNs is of energy consumption and computational complexity. Spiking Neural Networks (SNNs) are considered to be next-generation neural networks that are capable of doing complex deep learning applications at fraction of energy that is needed in current deep learning applications because of its similarity to biological neurons. However, SNN is still not able to match the classification accuracy of ANNs which poses a big challenge for wide acceptance of SNN in various applications as traditional learning methods like backpropagation are not possible in SNN. During training of a neural network the weight matrix is of the highest importance as it eventually decides the trajectory of learning. Currently, one existing solution is to just manually convert ANNs into SNNs to get weight matrix which doesn't focus on getting weight matrix from a small dataset and doesn't consider spiking neuron parameters. We propose a novel N-shot training methodology that is capable of providing a weight matrix for SNN and can give sufficient classification accuracy. The methodology not only provides the weight matrix but can perform training with a very small dataset(up to 1 image per class) and still obtain considerably higher accuracy. For a reduced MNIST dataset, the method can give an accuracy of 71.68% 10 images per class.

This thesis project achieves designing and comparing two parallel implementations for exhaustive grid search along a large model space to find the optimum mapping model for overlay predictions used in ASML lithography machines. The search algorithm leads to an effectively intractable problem as long as sequential implementation is concerned, but a parallel implementation using the technologies pro-vided by ASML High Performance Cluster (HPC) pave the way to tackle the challenge. A number of parallel execu-tion concepts have been developed using different frame-works that are exposed to the ASML HPC developer com-munity by the platform maintainers. Among these con-cepts, the most promising ones with respect to a defined set of criteria have been chosen to carry on with the implemen-tation effort. It has been shown that a PBS based Lab im-plementation can scale on HPC with a parallel efficiency of 66%, with most of the efficiency loss stemming from scheduler overhead. A second, Spark based Fab implementa-tion has an increased efficiency of 82%, paving a way for speedup of almost 1700x for a Spark cluster with 2048cores. Moreover, It has been shown experimentally that perfor-mance scales linearly over the model space dimensions. Baseline sequential implementation is estimated to take, by extrapolation, 2590 hours to execute on a single core for a typical model space use case. Refactoring the sequential implementation to utilize multiple CPU cores through mul-tiprocessing can drive execution down to 115 hours on a 24-core machine. Fab parallel implementation executes the same use case in 1.6 hours, enabling exploratory and itera-tive approaches to modeling for data scientists and domain experts.

Online searching for healthcare information has gradually become a widely used internet case. Suppose a patient suffers the symptom but is unsure of the action he needs to take, a self-diagnosis tool can help the patient identify the possible conditions and whether this patient needs to seek immediate medical help. However, the accuracy and quality of the service provided by those self-diagnosis tools are still disappointing and need further improvement. This thesis focuses on an automatic differential diagnosis task with a comprehensive evaluation of reinforcement learning methods. Also, we present a systematic method to simulate medically correct patients records, which integrates a standard symptom modeling approach called NLICE. In this way, we can bridge the gap between limited available patients records and data-driven healthcare methodologies. This project investigates both flat-RL methods and hierarchical RL in an automatic differential diagnosis setting and evaluates the performance of those two kinds of methods on simulated patients records. More specifically, the action space for the differential diagnosis task is inevitably large, so the flat-RL performs relatively poorly in complicated scenarios. The hierarchical RL method can split a complex diagnosis task into smaller tasks: it contains two-level of policy learning, and each low-layer policy imitates one medical specialty. Therefore hierarchical RL method increases the Top 1 success rate from 23.1\% in flat-RL method to 45.4\%.

Besides the advanced policy learning strategy, this thesis explores the ability of NLICE symptom modeling in distinguishing conditions that share similar symptoms. The experimental results experience increases in flat-RL and hierarchical RL models and finally achieve 36.2\% and 71.8\% Top 1 success rates, respectively. To further solve the sparse action space problem in the automatic diagnosis domain, the reward shaping algorithm is implemented in the reward configuration part. The average gained reward of hierarchical RL increases from -3.65 to 0.87. Additionally, we model the general demographic background of patients and utilize contextual information to perform the policy transformation strategy, which eliminates the miss classification problem in highly sex-age related diseases.

Current high-end medical X-ray intervention devices provide a tremendous amount of high-definition images per second. Combined with the additional inputs from the numerous auxiliary devices, processing and compositing the data in real-time quickly becomes an arduous engineering challenge. Furthermore, the critical nature of this application domain allows no room for error, whereas the process has to be simultaneously flexible enough to permit the unhindered work of the corresponding medical professional. Such medical imaging applications presently rely on complete hardware implementations of their processing pipelines and compositor engines, as opposed to earlier adopted paradigms of hardware-accelerated solutions. Said engines are usually realised in FPGA platforms due to their massively parallel computational capabilities and exceptional connectivity. However, given the vast amount of input streams arriving at the compositor's pipeline, switching and routing to available processing resources has remained a persistent issue. Present commercial solutions prove to be either too costly, too slow or too inflexible for developers to consider. On the other hand, academic literature centred around the subject is severely lacking. This thesis proposes a unique hardware architecture solution to mitigate the aforementioned problem. The proposed architecture, developed in collaboration with Philips Healthcare and TU Delft, exhibits an average end-to-end latency of 100 ns and a throughput of 7.2 Gb/s. Additionally, these results were realised under marginal resource utilisation, proving that such a switch can fit in the FPGA device and, subsequently, be developed as an integrated part of the compositor engine. Finally, the limited amount of reserved memory resources allowed for near-linear scalability of the proposed design should an increased amount of I/O devices be added; as well as dynamic portability should migration to smaller devices be a concern.

Pavlovian eyeblink conditioning is a powerful experiment used in the field of neuroscience to measure multiple aspects of how we learn in our daily life. To track the movement of the eyelid during an experiment, researchers traditionally made use of potentiometers or electromyography (EMG). More recently, the use of computer vision and image processing alleviated the need for these techniques, but currently employed methods require human intervention and are not fast enough to enable real-time processing. We selected a combination of face and landmark-detection algorithms in order to fully automate eyelid tracking, and accelerated them to make the first step towards an on-line implementation. Various different algorithms for face detection and landmark detection (eyelid detection) are analyzed and evaluated. Based on this analysis, two algorithms are identified as most suitable for our use case: the Histogram of Oriented Gradients (HOG) algorithm for face detection and Ensemble of Regression Trees (ERT) algorithm for landmark detection. These two algorithms are accelerated on GPU and CPU, achieving speedups of 1753× and 11.49×, respectively. A combination of these algorithms is successfully implemented for a real neuroscientific use-case: eyeblink response detection, achieving an overall application runtime of 0.533 ms per frame, which is 1067× faster than the sequential implementation. Furthermore, this accelerated implementation was used to generate a database of 1440 eyeblink responses during the conditioning experiment. We made use of multiple machine-learning techniques to analyze this database and concluded that there is a correlation between the asynchronicity of the eyelids and the eyeblink-response performance during the conditioning experiment.

The movement of whiskers in head-fixed mice is of high interest for neurological research, as it allows scientists to learn more about learning processes during active touch. However, manual tracking of whiskers in thousands of frames is not feasible, and reliable tracking of individual whiskers is not possible with the best current software available. In this work, a new system for the automatic tracking of whiskers in top-view videos of untrimmed, head-fixed mice is presented. The design of this system is based on a variety of image processing and computer vision algorithms. For each step, several alternatives have been considered and assessed. The best options have been combined and implemented in MATLAB. This new system, the Full-Whisker Tracking System (FWTS), detects the centerline of whiskers on each frame along their whole length with sub-pixel accuracy. The whiskers are defined by their angle, position, shape and length. FWTS uses these features to track and recognize whiskers over multiple frames in video segments with a frame rate of 1000 Hz. The system was tested on representative, challenging video segments from two experiments using different mice, and showed itself superior to the pre-existing system BWTT, by detecting on average 21.2% more whiskers, and with twice as much precision. In contrast to earlier systems, FWTS has been demonstrated reliably track individual whiskers in untrimmed mice. Furthermore, FWTS's processing time is on average 41.7% lower than that of BWTT. This thesis work shows that it is possible to track whiskers in untrimmed mice, even in the face of partial occlusions, and makes it possible to study the functioning of the intact whisker system of mice in unprecedented detail.

The amount of people dealing with dementia is rising globally. The amount of caretakers is, however, not. Therefore, technological aids are needed to support people dealing with dementia and relieve the stress on their caretakers. Current solutions provide tracking of people with dementia. Also, different robots exist that provide people with companionship. However, no solution exists that combines tracking and companionship capabilities. Therefore, the Smart Teddy is introduced. The Smart Teddy can track different indicators that indicate the progress of dementia and simultaneously provide the user with companionship through interaction. The goal of this thesis is to design a data acquisition system that acquires meaningful data that can be used for the development of algorithms that will autonomously determine the progress of dementia. To achieve this, a system with a Teddy and a Base station has been designed. The Teddy has a sound-, a carbon monoxide-, a smoke- and a movement sensor. Also, a real-time module is implemented to be able to assign the current time to the measurement data. Lastly, a GPS and GSM module is implemented to be able to track seniors in case they wander. In the Base station, a mmWave sensor is implemented that tracks the position, velocity, and direction of the persons present in the room. Also, a processor is implemented that gathers and stores the data from the mmWave sensor and the data from the Teddy which is sent via a LoRa connection. In addition, the designed system can store the collected data for more than one week. The collected data can be used by an expert in dementia to extract meaningful information about dementia progress, after that, an expert in digital signal processing is needed to develop algorithms that estimate the quality of life of a senior suffering from dementia.

With the increasing demand in home-care service to provide early intervention at the homes of seniors suffering from early stage dementia, the Smart Teddy prototype offers a technological solution to disburden caregivers, to promote and track the health and conditions of the senior and to prolong their independent life at home. The Smart Teddy is a project founded in 2018 by a research team of the Hague University of Applied Sciences. It is an interactive, companion robot - disguised as a toy dog - that serves as a therapeutic promoter while simultaneously monitoring the quality of life of the senior with pre-determined indicators. It consists of a Teddy to provide the interaction with the user and a Base Station for data processing and charging of the mount-in battery of the Teddy. The Power Operations and Distribution group carried out research on and developed suitable solutions to supply power to the Teddy with rechargeable batteries, to integrate controlled wireless charging of the battery for user-friendliness and to provide a streamlined power distribution throughout the Smart Teddy’s system. Based on an iterated program of requirements and a power budget analysis on the set of installed electronics, a design is implemented for the power system of the Smart Teddy. A design sequence is followed consisting of four stages: (1) battery selection, (2) charger selection, (3) power conversion and distribution, and (4) safety and failure protection. A power system is developed for the Smart Teddy that is able to supply power with lithium-ion batteries with a battery life of at least 12 hours providing a battery capacity of 25.16 Wh. Thereafter, the installed batteries located in the Teddy can be charged wirelessly by placing the Teddy on the Base Station (a dog bed) to reinforce the less robot-like and a more natural look of the Teddy. Furthermore, this system ensures that all electronic modules with different operating voltages and current draws are provided with the necessary power specifications through power-sharing paths and the usage of power converters. Lastly, safety measures and failure protection methods are developed to ensure the safety of the user through the usage of fuses, switches and, cable and PCB management. The design has been verified using the appropriate verification methods where the program of requirements is used as a guideline and assessment tool. The Power Operations and Distribution is largely complying with the program of requirements and is performing according to the predetermined functionalities. Consequently, the power system of the Smart Teddy is integrated in a real, spatial prototype, namely in a toy dog (the Teddy) and its dog bed (the Base Station).

The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC.
A fully automatic scripted flow is described, constructing an optimized, error-free ASIC. The design area is limited to 3.5 um², to allow it to be manufactured with the cheapest 65 nm prototyping run available at IMEC. In order to achieve this small design area, a new 24-port register file design has to be devised. In its current state, it is implemented using standard logic cells. Clever optimizations involving cell padding and minimum overhead power routing are necessary to reduce a total routing overcongestion from 7% to zero.
This implementation is expected achieve a clock speed of 141 MHz, only limited by the ρ-VEX reconfiguration logic. By lowering the frequency to 100 MHz, the energy dissipation is reduced by 96%, to a total of 367 uW/MHz. This is comparable to similar VLIW designs. Using LVDS communication clocked at four times the core frequency, a data bandwidth of 4 Gbit/s is achieved using only 26 external pins. This allows the main data and instruction memory to reside off-chip.
To ensure a correct design, it is verified using DRC, LVS, and ERC. For improved reliability, IR-drop is kept within 1% of the core voltage, using minimal power routing. Furthermore, the effect of electromigration is kept extremely low such that the mean time to failure on nets is 90 years.
The scripted flow will aid in prototyping, allowing accurate estimates to be calculated in a mere 7% of the original time. Proposals for a future design are expected to reduce the register file area and power dissipation by more than 40%. By improving the pipeline and shortening the critical path, a two to four fold improvement in clock speed can be expected, without adversely affecting power dissipation.

Transferring composite data structures with variable-length fields often requires designing non-trivial protocols that are not compatible between hardware designs. When each project designs its own data format and protocols the ability to collaborate between hardware developers is diminished, which is an issue especially in the open-source community. Because the high-level meaning of a protocol is often lost in translation to low-level languages when a custom protocol needs to be designed, extra documentation is required, the interpretation of which introduces new opportunities for errors.

The Tydi specification (Tydi-spec) was proposed to address the above issues by codifying the composite and variable-length data structures in a type and providing a standard protocol to transfer typed data among hardware components. The Tydi intermediate representation (Tydi-IR) extends the Tydi-spec by defining typed interfaces, typed components, and connections among typed components.

In this paper, we propose Tydi-lang, a high-level hardware description language (HDL) for streaming designs. The language incorporates Tydi-spec to describe typed streams and provides templates to describe abstract reusable components. We also implement an open-source compiler from Tydi-lang to Tydi-IR. We leverage a Tydi-IR to VHDL compiler, and also present a simulator blueprint to identify streaming bottlenecks. We show several Tydi-lang examples to translate high-level SQL to VHDL to demonstrate that Tydi-lang can efficiently raise the level of abstraction and reduce design effort.

Current brain simulators do no scale linearly to realistic problem sizes (e.g. >100,000 neurons), which makes them impractical for researchers. The goal of the thesis is to explore the use of true multi-GPU acceleration on computationally challenging brain models and to assess the scalability of such models given sufficient access to multi-node acceleration platforms. The brain model used is a state-of-the-art, extended HodgkinHuxley, biophysically- meaningful, three-compartmental model of the inferior-olivary nucleus. Not only the simulation of the cells, but also the setup of the network is taken into account when designing and benchmarking the multi-GPU version. For network sizes varying from 65K to 4M cells, 10, 100 and 1000 synapses per neuron are simulated. These simulations are executed on 8, 16, 32 and 48 GPUs. A Gaussian-distributed network of 4 million cells with a density of 1,000 synapses per neuron executed on 48 GPUs, is setup and simulated in 465.69 seconds, of which the cell-computation phase takes 4.57 seconds, obtaining a speedup of 50 times the execution time on a single GPU. A uniform-distributed network of same size and density is setup and simulated in 889.89 seconds of which the cell-computation phase takes 10.09 seconds, obtaining a speedup of 8 times the execution on a single GPU. For the implemented design, the inter-GPU communication becomes the major bottleneck, as latency increases when the sent packet sizes increase. This communication overhead does not dominate the overall execution while scaling network sizes is tractable. This scalable design gives a good prospect for neuroscientists, proving that large network-size simulations are possible, using a multi-GPU setup.

Unitary Decomposition is an algorithm for translating a unitary matrix into many small unitary matrices, which correspond to a circuit that can be executed on a quantum computer. It is implemented in the quantum programming framework of the QCA-group at TU Delft: OpenQL, a library for Python and C++. Unitary Decomposition is a necessary part in Quantum Associative Memory, an algorithm used in Quantum Genome Sequencing. The implementation is faster than other known implementations, and generates $3*2^{n-1}*(2^n-1)$ rotation gates for an n-qubit input gate. This is not the least-known nor the theoretical minimum amount, and there are some optimizations that can still be done to make it closer to these numbers.

Fast sequencing and analysis of (microorganism, plant or human) genomes will open up new vistas in fields like personalised medication, food yield and epigenetic research. Current state-of-the-art DNA pattern matching techniques use heuristic algorithms on computing clusters of CPUs, GPUs and FPGAs. With genomic data set to eclipse social and astronomical big data streams within a decade, the alternate computing paradigm of quantum computation is explored to accelerate genome-sequence reconstruction. The inherent parallelism of quantum superposition of states is harnessed to design a quantum kernel for accelerating the search process. The project explores the merger of these two domains and identifies ways to fit these together to design a genome-sequence analysis pipeline with quantum algorithmic speedup. The design of a genome-sequence analysis pipeline with a quantum kernel is tested with a proof-of-concept demonstration using a quantum simulator.

This thesis explores the use of machine learning techniques in an effort to increase insurer competitiveness. It asks whether it is possible to accurately estimate the expected financial loss of a given insurance contract and how this information can be used to gain a competitive edge in the business. To answer these questions, some basic principles of insurance are introduced, with a focus on statistical modeling. Furthermore, potentially successful algorithms and techniques are described, like ordinary least squares, generalized linear models (GLMs), generalized additive models, clustering, random forests and gradient boosting trees. It is shown that theory that was originally developed for GLMs, can easily be generalized to other methods, chiefly gradient boosting, with often better results. A new form of evaluation is introduced that helps to rate the efficiency of an insurance portfolio. This, and other metrics are finally applied to several designed models to demonstrate their effectiveness.

The ever-increasing demand for computing has led to the need for specialized heterogeneous hardware, and the frameworks required to utilize them. Besides the traditional central processing units, more and more programs will make use of specialized hardware to accelerate computations. However, the increase in computing also leads to shorter mean time between failures. In this thesis, we apply fault tolerance to Portable Computing Language (PoCL), an open-source implementation of the OpenCL standard. We show that our solution is easy to apply to existing programs making use of PoCL/OpenCL and is able to greatly reduce the total number of errors visible to the end user. Our solution can be used on any device supported by PoCL and provides a low overhead, given that the hardware requirements are met.

Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. This provides a higher-level method for defining interfaces between components as opposed to existing bit- and byte-based interface specifications.

In this thesis, an open-source intermediate representation (IR) is introduced which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi’s streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system.

The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior.

To demonstrate this IR, a grammar, parser, and query system have been created, and paired with a backend targeting VHDL.

Low latency Convolutional Neural Network (CNN) inference research is gaining more and more momentum for tasks such as speech and image classications. This is because CNNs have the ability to surpass human accuracy in classication of images. For improving the measurement setup of gravitational waves, low latency CNNs inference are researched. The CNN needs to process data from images to enable certain automatic controls for the control system. The data of these images need to be processed within 0.1 ms from the moment of taking the image to the control system obtaining the result of a deep neural network. Hardware acceleration is needed to reduce the execution latency of the network and reach the 0.1 ms requirement. Field-Programmable Gate Arrays (FPGAs) in particular have the ability to provide the needed acceleration. This is because FPGAs have the ability to create highly customised layers of the network and obtain the lowest possible latency. To reduce the design eort and complexity of the machine learning design, Xilinx introduced the FINN (Fast, Scalable Quantized Neural Network Inference on FPGAs) framework. FINN is an end-to-end deep learning framework that generates data ow-style architectures customised for each network. To establish if FINN can create the required ultra low latency CNN, some of FINN pretrained networks are used. The rst neural network investigated is the Tiny Fully Connected (TFC) network. The TFC network is a multilayer perceptron (MLP) for MNIST classication with three fully connected layers. The other network investigated is the convolutional neural network named CNV. CNV is a derivative of the VGG16 topology. The VGG16 topology is used for deep learning image classication problems with multiple convolutional layers. By using the analysis tools included with FINN, it can be determined if FINN is able to create the required ultra low latency CNN. The TFC network can be parallelised to a total of 5 expected cycles, with 1 expected cycle per layer. One cycle for the input quantization to standalone thresholding, one for the output layer and nally three for the fully connected layers. For the CNV network on the other hand, the initial convolution layer is unable to go below 8196 expected cycles, because of certain bottlenecks with FINN. These bottlenecks occur because of how FINN implements certain layers, moreover because certain layers can simply no longer be parallelised to lower the latency of that layer. To see if the CNV could achieve the latency requirements, a software emulation of the execution of the network has been done. This emulation showcased that by continuously increasing the parallelisation parameters, together with increasing clock frequencies, it is possible to create an ultra low latency pipeline of a CNN. This conguration has 45866 expected total cycles for the network, its expected cycles for the slowest layer is 8196 and needs a minimum frequency of 200 MHz. With those conguration it is possible to create a pipeline that has a latency of lower than 0.1 ms.