Synthetic image generation involves the creation of artificially generated images that are indistinguishable from real ones. Conventional simulation-based image synthesis approaches suffer from intensive computational and memory throughput demands associated with physically accurate ray tracing through volumetric datasets. In this work, we propose an FPGA-based accelerator architecture capable of handling the computations required to simulate physically accurate X-ray images in real time. In addition, an algorithm is developed that can calculate the path of an X-ray through a phantom representing a physical model. To ensure real-time performance, a parallel accelerator architecture is proposed using a chain of accelerator kernels combined with High Bandwidth Memory architecture, which can simulate many rays concurrently, addressing the computational and memory throughput demands associated with simulationbased X-ray image generation. Performance evaluation of the simulation on an AMD Alveo U50 Data Accelerator card shows that an average speed-up of $12 \mathrm{x}$ over CPU-based implementations is possible, and allows for realtime image synthesis at a frame rate of 60 images $/ \mathrm{s}$. These findings highlight the advantages of FPGA acceleration for deterministic, high-speed synthetic image generation.

While modern HDLs such as Chisel (Constructing Hardware In a Scala Embedded Language) significantly improve the process of design entry, debugging these designs is often problematic, because the tools that aid debugging operate on translated code rather than the original HDL. Furthermore, engineers often resort to manual waveform debugging, undermining productivity gains promised by such a language. We present ChiselTrace, an open-source tool for Chisel that is capable of (dynamic) program slicing and automatic signal dependency tracing, allowing faults to be more easily traced back to their root cause. Where prior work focuses on data-flow analysis at the (compiled) Verilog level, ChiselTrace functions at the Chisel source level. Contributions include: modifications to the Chisel library to enable post-simulation analysis; a library capable of dynamic program slicing and dependence graph generation; and a front-end dependency graph viewer. We demonstrate debugging capabilities by tracing an injected fault in the ChiselWatt processor back to the source. We observe that using ChiselTrace's dynamic program dependence graph, the number of lines of code relevant to the fault path is reduced significantly. Project repository: https://github.com/jarlb/chiseltrace

As dedicated hardware is becoming more prevalent in accelerating complex applications, methods are needed to enable easy integration of multiple hardware components into a single accelerator system. However, this vision of composable hardware is hindered by the lack of standards for interfaces that allow such components to communicate. To address this challenge, the Tydi standard was proposed to facilitate the representation of streaming data in digital circuits, notably providing interface specifications of composite and variable-length data structures. At the same time, constructing hardware in a Scala embedded language (Chisel) provides a suitable environment for deploying Tydi-centric components due to its abstraction level and customizability. This article introduces Tydi-Chisel, a library that integrates the Tydi standard within Chisel, along with a toolchain and methodology for designing data-streaming accelerators. This toolchain reduces the effort needed to design streaming hardware accelerators by raising the abstraction level for streams and module interfaces, hereby avoiding writing boilerplate code, and allows for easy integration of accelerator components from different designers. This is demonstrated through an example project incorporating various scenarios where the interface-related declaration is reduced by 6-14 times. Tydi-Chisel project repository is available at https://github.com/abs-tudelft/Tydi-Chisel.