Intracortical brain computer interfaces hold the potential to revolutionize neurotherapeutics, but they must overcome technological challenges such as the high data rates generated by high-channel-count neural sensors and the stringent power and volume constraints of implantable devices. In addition, the brain-wide coverage needed for a deeper understanding of brain processes challenges the synchronization between distributed neural sensors and the central neural hub. To address these challenges, we present a deterministic-latency and power-efficient serializer–deserializer (SerDes) telemetry network that effectively mitigates the synchronization issue under strict power and volume constraints. The serializer on the sensor side employs event-based sampling and a packet-based address-event representation transmission protocol, achieving a low power consumption of only 127 µW and a low latency variation <10 µs. A crystal-free clock source is employed on the sensor side to minimize power consumption, with serialized data encoded using Manchester coding scheme. The deserializer on the hub handles the bit period uncertainty by counting and extracting the bit period of received data with a clock only ∼2.2× faster than the serializer clock. The proposed counting-based Manchester decoder achieves a wide frequency coverage up to 204 000 ppm of frequency variation. The deserializer achieves a measured Manchester decoding bit error rate (BER <10−6), with a total estimated power consumption below 415 µW. The SerDes performance has been validated with in vivo pre-recorded data, demonstrating a compression ratio greater than 7, while preserving a high signal fidelity with an average RMSE <6 µVRMS.

This paper introduces SENMap, a mapping and synthesis tool for a scalable energy efficient neuromorphic computing architecture frameworks. SENECA a flexible architectural design optimized for executing edge AI SNN/ANN inference applications efficiently. To speed up the silicon tapeout and chip design for SENECA, an accurate emulator SENSIM was designed. While SENSIM supports direct mapping of SNNs on neuromorphic architectures, as the SNN/ANN grow in size, achieving optimal mapping for objectives like energy, throughput, area, and accuracy becomes challenging. This paper introduces SENMap, flexible mapping software for efficiently mapping large SNN/ANN applications onto adaptable architectures. SENMap considers architectural, pretrained SNN/ANN realistic examples, and event rate-based parameters and is open-sourced along with SENSIM to aid flexible neuromorphic chip design before fabrication. Experimental results show SENMap enables 40 percent energy improvements for a baseline SENSIM operating on timestep asynchronous mode of operation. SENMap is designed in such a way that it facilitates mapping large spiking neural networks for future modifications as well.

Neuromorphic processors promise low-latency and energy-efficient processing by adopting novel brain-inspired design methodologies. Yet, current neuromorphic solutions still struggle to rival conventional deep learning accelerators' performance and area efficiency in practical applications. Event-driven data-flow processing and near/in-memory computing are the two dominant design trends of neuromorphic processors. However, there remain challenges in reducing the overhead of event-driven processing and increasing the mapping efficiency of near/in-memory computing, which directly impacts the performance and area efficiency. In this work, we discuss these challenges and present our exploration of optimizing event-based neural network inference on SENECA, a scalable and flexible neuromorphic architecture. To address the overhead of event-driven processing, we perform comprehensive design space exploration and propose spike-grouping to reduce the total energy and latency. Furthermore, we introduce the event-driven depth-first convolution to increase area efficiency and latency in convolutional neural networks (CNNs) on the neuromorphic processor. We benchmarked our optimized solution on keyword spotting, sensor fusion, digit recognition and high resolution object detection tasks. Compared with other state-of-the-art large-scale neuromorphic processors, our proposed optimizations result in a 6× to 300× improvement in energy efficiency, a 3× to 15× improvement in latency, and a 3× to 100× improvement in area efficiency. Our optimizations for event-based neural networks can be potentially generalized to a wide range of event-based neuromorphic processors.

In this paper, we present SENSIM, which is an open-source simulator designed specifically for the SENECA neuromorphic processor. This simulator is unique in that it combines features from both hardware-specific and hardware-agnostic spiking neural network simulators, resulting in a hybrid event-driven and time-step-driven simulation approach. This allows for flexibility between accuracy and speed during different stages of simulation. Our work highlights the open-source SENSIM platform, which enables the mapping of large-scale SNN/DNN models to the SENECA cores, as well as the benchmarking of crucial KPIs such as power and latency estimations.