The development of the Spiking Neural Network (SNN) offers great potential in combination with new types of event-based sensors, by exploiting the embedded temporal information. When combined with dedicated neuromorphic hardware it enables ultra-low power solutions and local on-chip learning. This work implements and presents a viable architecture and training methodology to detect and classify audio data using Spiking Neural Networks. The architecture consists of two core components: the first component is an auditory front-end that performs low-level feature extraction. The second component is the SNN classifier supported by the spike encoder and decoder. The results show that the encoder has a major impact on the overall performance of the network. The temporal-based network is trained with help of common training methods, both supervised and unsupervised. The performance of the network is validated under both clean and different levels of noisy conditions. The impact on classification performance is analyzed and compared with traditional non-spiking Artificial Neural Networks. This in terms of classification accuracy, estimate energy consumption, and latency of inference. The proposed architectures achieve a max accuracy of 97.0% under ideal conditions. This is comparable to other non-spiking artificial neural networks, which require significantly more energy for inference. The implementation demonstrates that the architecture is a viable solution for detecting and classifying audio data.

As we move towards edge computing, not only low power but concurrently, critical timing is demanded from the underlying hardware platform. Spiking neural networks ensure high performance and low power when run on specialized architectures like neuromorphic hardware. However, the techniques in use to configure these neural networks on massively parallel neuromorphic crossbar arrays remain sparsely explored. This motivates the research on how neural network topologies encompassing spiking architectures can be configured on a neuromorphic hardware. In this thesis, a unique placement algorithm is devised to map diverse and complex neural network architectures on a connectivity-constrained array with thousands of processing elements(PEs) within seconds. Wide spectra of SNNs with varying complexity are investigated to evaluate the feasibility of mapping on the target neuromorphic architecture involving unique connectivity constraints. The performance of the proposed ALAPIN mapper is validated through time-to-solution for the surveyed SNN schemes with varying network sizes and diverse complexity measures. Experiments show that simple networks converge within 10 milliseconds. With limited resources and as the network architectural complexity increases, hardware constraints become overwhelming to achieve placement solution within a decent time frame. Further experiments are carried out to estimate the resource utilization of each candidate SNN for varying network sizes on target hardware. Liquid state machines use a greater number of synapses for a same number of neurons than the rest of the candidates, with approximately 100% neurons, 30% input resources, and 20% synapses on target hardware.

Neurons in Spiking Neural Networks (SNNs) communicate through spikes, similarly that neurons in the brain communicate, thus mimicking the brain. The working of SNNs is temporally based, as the spikes are time-dependent. SNNs have the benefit to perform continual classification, and are inherently more low-power than other Artificial Neural Networks (ANNs). Both the SNNs and other ANNs need to be trained to perform specific tasks. There are several types of methodologies to train SNNs, but there is yet no silver bullet. Backpropagation algorithms can train other ANNs, but SNNs cannot be trained using this algorithm since the spikes are not differentiable. Methods like Spike Timing Dependent Plasticity (STDP) or Liquid State Machine (LSM) have their limits. Where the complexity of SNNs depends on the dataset, the number of neurons, and other factors. There were currently no known SNN implementations for the given gesture, achieving near state-of-the-art results. The problem with the dataset is that usually no gesture is performed in front of the . The datasets contain noise, and some data samples belong to two or more classes simultaneously. The objective of this work is to develop an architecture and training methodology, that allows the classification of the dataset using SNNs. This work presents a novel, architectural training methodology Suino, which addresses the above problems. The architecture consists of two components: the first is the spatial classifier, and the second component is the temporal classifier. The frames from the dataset are filtered in the first stage, i.e. the spatial classifier. The output of the spatial classifier is the input for the temporal classifier, which deals with the temporal properties of the data. Suino does not provide false positives, that is the neurons do not spike on the input dataset if the input dataset does not belong to any of the trained classes; hence the method is robust. The training method is built around these components, existing of different classical training methods: backpropagation, clustering, or any other consisting of fixed threshold method for auto label correction. The second stage consists of a temporal classification method, trained using the Tempotron learning rule. The time-series dataset of gestures validated Suino. On the test set, the baseline method had an accuracy of 97.0% with 35K parameters, while the presented method had an accuracy of 90.87% with 21K parameters. Hence, the method is more robust against false detections and continuously performs classification.

Traditional Artificial Neural Networks(ANNs)like CNNs have shown tremendous opportunities in various domains like autonomous cars, disease diagnosis, etc. Proven learning algorithms like backpropagation help ANNs in achieving higher accuracy. But there is a serious challenge with the increasing popularity of traditional ANNs is of energy consumption and computational complexity. Spiking Neural Networks (SNNs) are considered to be next-generation neural networks that are capable of doing complex deep learning applications at fraction of energy that is needed in current deep learning applications because of its similarity to biological neurons. However, SNN is still not able to match the classification accuracy of ANNs which poses a big challenge for wide acceptance of SNN in various applications as traditional learning methods like backpropagation are not possible in SNN. During training of a neural network the weight matrix is of the highest importance as it eventually decides the trajectory of learning. Currently, one existing solution is to just manually convert ANNs into SNNs to get weight matrix which doesn't focus on getting weight matrix from a small dataset and doesn't consider spiking neuron parameters. We propose a novel N-shot training methodology that is capable of providing a weight matrix for SNN and can give sufficient classification accuracy. The methodology not only provides the weight matrix but can perform training with a very small dataset(up to 1 image per class) and still obtain considerably higher accuracy. For a reduced MNIST dataset, the method can give an accuracy of 71.68% 10 images per class.

One of the challenges of neuromorphic computing is efficiently routing spikes from neurons to their connected synapses. The aim of this thesis is to design a spike-routing architecture for flexible connections on single-chip neuromorphic systems. A model for estimating area, power consumption, memory, spike latency and link utilisation for neuromorphic spike-routing architecture is described. This model leads to the proposal for a new spike-routing architecture with a hybrid addressing scheme and a novel synaptic encoding scheme. The proposed architecture is implemented in a SystemC simulation tool with a supporting tool for encoding arbitrary SNN topologies for the synapse encoding scheme. Running the simulations with synthetic benchmarks and a handwriting recognition SNN shows that the proposed architecture is memory-efficient and provides low latency spike-routing with high synaptic activation concurrency.

Recent trends in platforms for the consumer market increased the need for low-power and reliable classification engines. Spiking Neural Network (SNN) is a new technology that promises to deliver 4 orders of magnitude more performance per watt than competing solutions. Moreover, the adoption of RADAR for gesture detection provides higher reliability compared to image sensors. However, no accepted topology for a temporal SNN classifier focusing on RADAR data exists. In addition, previous research did not account for several design limitations necessary to export the design in analog hardware. In this work, we explore the possible SNN topologies and propose a Liquid State Machine (LSM) with fully-supervised readout, suitable to be exported to a mixed-signal neuron array. A complete parametric model of the architecture and learning rule has been implemented in a simulation environment. Following, the design space was explored in search for the optimal operating region. By analysing the results, we: (i) highlight and explain the effects of several parameters and the trade-off between accuracy and power consumption; (ii) emphasize the need for a good balance between global excitation and inhibition in the LSM; (iii) suggest that the limitations of the proposed design point to the importance of an adequate feature extraction for a stable LSM behaviour and to the unpredictable nature of the SNN backpropagation algorithm, caused by the non differentiability of the spike signals.

Spiking Neural Networks have opened new doors in the world of Neural Networks. This study implements and shows a viable architecture to detect and classify blob-like input data. An architecture consisting of three parts a region proposal network, weight calculations, and the classifier is discussed and implemented. The region proposal network is build based on a blob detecting Laplacian of Gaussian function. The architecture is tested and verified on the Multi MNIST dataset that is generated based on the MNIST dataset that consists of handwritten digits. Results show that, on average, the region proposal network can locate the blobs in the input with an accuracy of within a single pixel distance from the ground truth. Two different ways of decoding the rate data coming from the region proposal network where discussed the Peak based decoder could propose regions even if these regions are situated closely together. A Center of Mass decoder is slightly more accurate than the Peak based decoder but at a higher computational cost and performance degradation when the regions are close together. The region proposal network at worst only accounts for 3.19% of inaccuracy. The implementation shows that the architecture is a viable way of detecting and classifying multiple objects within the input. The data shows that the region proposal network itself is a feasible way of detecting blob-like objects within its input.

Cardiovascular diseases are the leading cause of death in the devel- oped world. Preventing these deaths, require long term monitoring and manual inspection of ECG signals, which is a very time consum- ing process. Consequently, a wearable system that can automatically categorize beats is essential.
Neuromorphic machines have been introduced relatively recently in the science community. The aim of these machines is to emulate the brain. Their low power design makes them an optimal choice for a low power wearable ECG classifier.
As features are crucial in any machine learning system, this thesis aims at proposing an energy efficient feature extraction algorithm for ECG arrhythmia classification using neuromorphic machines. The feature extraction algorithm proposed in this thesis consists of the merger of a low power feature detection and a feature selection algorithm. Also, different network configurations have been investigated to achieve classification using an LSM architecture. The resulting system can accurately cluster seven beat types, has an overall classification rate of 95.5%, and consumes an estimate of 803.62 nW.

The Self-Organizing Map (SOM) is an unsupervised neural networktopology that incorporates competitive learning for the classicationof data. In this thesis we investigate the design space of a system incorporating such a topology based on Spiking Neural Networks (SNNs), and apply it to classifying electrocardiogram (ECG) beats. We present novel insights into the characterization of the SOMand its encapsulating system by exploring conguration parameterssuch as learning rate, neuron models, potentiation and depression ratios, and synaptic conductivity parameters by performing high-level architectural simulations of the system whose SNN is developed withthe aim of being implemented using power ecient neuromorphichardware. Due to the amount of manual work needed to monitor and analyze ECG signals when diagnosing cardiovascular problems, and because it is the leading cause of death in the world, an automated, realtime, and low power detection & classication system is essential. Unsupervised and in realtime, this system performs beat detection with an average True Positive Rate (TPR) of 99.10% and a Positive Predictive Value (PPV) of 99.58% and classication of 500 detected beats with a Multidimensional Scaling Error (EMDS) of 0.0169 and a beat recognition percentage of 100%.

As technology scaling enters the nanometer regime, device aging effects cause quality and reliability issues in CMOS Integrated Circuits (ICs), which in turn shorten its lifetime. Evaluating system aging through circuit simulations is very complex and time consuming. In this thesis, a framework is proposed, which allows for the evaluation of long-term aging effects of ICs and the corresponding measures to counteract premature failure. The focus of this work lies in the abstraction of low-level aging models to system-level models, in order to facilitate swift high-level simulation, without any knowledge of underlying circuit dynamics. Two major aging mechanisms, namely Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) degradation are considered for analysis. System-level aging management is performed with the prototype of a System-on-Chip (SoC) including a Management Unit (MU), which counteracts aging by employing Dynamic Voltage Scaling (DVS), Dynamic Frequency Scaling (DFS), and Adaptive Body Biasing (ABB). The simulation platform prototype is based on System-C AMS and a 65-nm technology library. This SoC simulation computes path delay using characterized models, which represent the aged behaviour of individual circuit elements. Results show that the obtained values are within 2% of circuit-level simulation values at the cost of a simulation time which is 15x lesser than conventional circuit simulators (e.g. Cadence NCSim).