Traditional Artificial Neural Networks(ANNs)like CNNs have shown tremendous opportunities in various domains like autonomous cars, disease diagnosis, etc. Proven learning algorithms like backpropagation help ANNs in achieving higher accuracy. But there is a serious challenge with the increasing popularity of traditional ANNs is of energy consumption and computational complexity. Spiking Neural Networks (SNNs) are considered to be next-generation neural networks that are capable of doing complex deep learning applications at fraction of energy that is needed in current deep learning applications because of its similarity to biological neurons. However, SNN is still not able to match the classification accuracy of ANNs which poses a big challenge for wide acceptance of SNN in various applications as traditional learning methods like backpropagation are not possible in SNN. During training of a neural network the weight matrix is of the highest importance as it eventually decides the trajectory of learning. Currently, one existing solution is to just manually convert ANNs into SNNs to get weight matrix which doesn't focus on getting weight matrix from a small dataset and doesn't consider spiking neuron parameters. We propose a novel N-shot training methodology that is capable of providing a weight matrix for SNN and can give sufficient classification accuracy. The methodology not only provides the weight matrix but can perform training with a very small dataset(up to 1 image per class) and still obtain considerably higher accuracy. For a reduced MNIST dataset, the method can give an accuracy of 71.68% 10 images per class.

Conversion from digital information to spike trains is needed for Spiking Neural Networks. Moreover, it is one of the most important steps for Spiking Neural Networks. This conversion could lead to much information loss depending on which encoding algorithm is used. Another major problem that can occur in a specific use-case is the limited bandwidth for the spikes that get generated through the encoding algorithm. In this thesis, we propose population Step Forward Encoding algorithm. This algorithm takes the signal encoding accuracy of Step Forward encoding algorithm and makes it into a population, generating multiple spike trains. This allows a higher threshold to encode a large part of the signal, increasing the efficiency. We show that population Step Forward Encoding algorithm doesn't just work good for the signal encoding accuracy, but also for the classification accuracy. Moreover, population Step Forward Encoding algorithm does not only have a high efficiency with a low spike count, it can also achieve higher efficiency with higher spike count. Thus, population Step Forward can make most use of a limited bandwidth of spikes.

Neuromorphic electronic systems have used asynchronous logic combined with continuous-time analog circuits to emulate neurons, synapses, and learning algorithms. It is attractive because of its low power consumption and feasible implementation. Typically, the neuron firing rates are lower than the modern digital systems. Thus, the endpoints of neuromorphic electronic systems are clusters of neurons instead of individual neurons. Address event representation (AER) was proposed in 1991 to multiplex communication for a cluster of neurons into an individual communication channel. AER circuits provide multiplexing/demultiplexing functionality for spikes that are asynchronously generated by/delivered to an array of individual neurons. Asynchronous techniques are not only used in neuromorphic electronic systems, but also widely used in globally asynchronous and locally synchronous (GALS) SoCs, or SoCs with full-asynchronous solutions. However, commercial tools on the market do not support designing asynchronous circuits, making the circuits cannot be adopted easily by most products. This thesis aims at addressing the challenge by providing an asynchronous library establishment strategy. The strategy uses SR-latches as standard asynchronous cells together with logic gates to build an AER communication circuit. With the strategy, the performance of using a modified traditional arbiter in the AER transmitter can be compared favourably with using state-of-the-art arbiters. A back-end flow and a verification flow are developed to evaluate the performance of the design as well as to check the feasibility of the strategy. The proposed 32-bit AER transmitter under TSMC 28nm CMOS technology sacrifices area and power to achieve better timing performance, where the modified arbiter inside has an 11.54% better response time than the arbiter who used to be the best in an old comparison.

Neurons in Spiking Neural Networks (SNNs) communicate through spikes, similarly that neurons in the brain communicate, thus mimicking the brain. The working of SNNs is temporally based, as the spikes are time-dependent. SNNs have the benefit to perform continual classification, and are inherently more low-power than other Artificial Neural Networks (ANNs). Both the SNNs and other ANNs need to be trained to perform specific tasks. There are several types of methodologies to train SNNs, but there is yet no silver bullet. Backpropagation algorithms can train other ANNs, but SNNs cannot be trained using this algorithm since the spikes are not differentiable. Methods like Spike Timing Dependent Plasticity (STDP) or Liquid State Machine (LSM) have their limits. Where the complexity of SNNs depends on the dataset, the number of neurons, and other factors. There were currently no known SNN implementations for the given gesture, achieving near state-of-the-art results. The problem with the dataset is that usually no gesture is performed in front of the . The datasets contain noise, and some data samples belong to two or more classes simultaneously. The objective of this work is to develop an architecture and training methodology, that allows the classification of the dataset using SNNs. This work presents a novel, architectural training methodology Suino, which addresses the above problems. The architecture consists of two components: the first is the spatial classifier, and the second component is the temporal classifier. The frames from the dataset are filtered in the first stage, i.e. the spatial classifier. The output of the spatial classifier is the input for the temporal classifier, which deals with the temporal properties of the data. Suino does not provide false positives, that is the neurons do not spike on the input dataset if the input dataset does not belong to any of the trained classes; hence the method is robust. The training method is built around these components, existing of different classical training methods: backpropagation, clustering, or any other consisting of fixed threshold method for auto label correction. The second stage consists of a temporal classification method, trained using the Tempotron learning rule. The time-series dataset of gestures validated Suino. On the test set, the baseline method had an accuracy of 97.0% with 35K parameters, while the presented method had an accuracy of 90.87% with 21K parameters. Hence, the method is more robust against false detections and continuously performs classification.

Spiking neural networks (SNN), as the third-generation artificial neural network, has a similar potential pulse triggering mechanism to the biological neuron. This mechanism enables the spiking neural network to increase computing power compared to the traditional artificial neural network to process complex information. However, a large number of interconnection resources is required. This requirement is highly consistent with the characteristics of the network on chip (NoC). This thesis is aimed at developing a scalable cycle-accurate simulator based on Noxim, which provides a configurable NoC that can simulate neuron-to-neuron communication for delivering spiking traffic. This simulator achieves several configurable metrics including topology and routing schemes, network size, the number of channels, and neuron mapping methods. This thesis then evaluates the effects of these metrics on performance for two kinds of traffic patterns. To take power consumption and area into account, this thesis also provides an approximate estimate of area and power consumption for trade-offs in the early-design stage.

Mobile devices are getting increasingly powerful, becoming compatible
for an ever increasing set of functionality. Applications based around
neural networks however still have to offload parts of their computations
to the cloud since current Artificial Neural Networks (ANNs) are
still too computationally expensive for any practical standalone use in
energy constrained mobile devices. Developments in the next generation
of ANN: Spiking Neural Network (SNN), are expected to bring
neural networks directly to the edge. Even though SNNs are becoming
a reality, they can not (yet) effectively operate on raw sensory input
data. For this, a preprocessing algorithm can be used to extract low-level
features in an efficient way to boost the neural network efficiency.
A parallel can be found in biology with the cochlea that, for audio,
provides preprocessing for the brain. Recent research has shown that
an SNN is capable of reaching high classification accuracy when combined
with an biologically plausible audio preprocessing stage. To be
of interest for edge-computing it however also needs to be area and
energy efficient. This thesis will provide the first steps in researching
the optimal configuration of a specific audio preprocessing algorithm
by mapping its current software simulation to embedded hardware.
For this purpose the software simulation is analyzed and an efficient
hardware implementation is designed. For evaluation a prototype,
and its hardware constrained simulation, is developed and optimized.

The development of the Spiking Neural Network (SNN) offers great potential in combination with new types of event-based sensors, by exploiting the embedded temporal information. When combined with dedicated neuromorphic hardware it enables ultra-low power solutions and local on-chip learning. This work implements and presents a viable architecture and training methodology to detect and classify audio data using Spiking Neural Networks. The architecture consists of two core components: the first component is an auditory front-end that performs low-level feature extraction. The second component is the SNN classifier supported by the spike encoder and decoder. The results show that the encoder has a major impact on the overall performance of the network. The temporal-based network is trained with help of common training methods, both supervised and unsupervised. The performance of the network is validated under both clean and different levels of noisy conditions. The impact on classification performance is analyzed and compared with traditional non-spiking Artificial Neural Networks. This in terms of classification accuracy, estimate energy consumption, and latency of inference. The proposed architectures achieve a max accuracy of 97.0% under ideal conditions. This is comparable to other non-spiking artificial neural networks, which require significantly more energy for inference. The implementation demonstrates that the architecture is a viable solution for detecting and classifying audio data.

This dissertation describes an approach to building a self-timed asynchronous pulse-mode serial link circuit. Unlike asynchronous handshake circuits or synchronous circuits, this design style does not require any feedback control blocks, which can increase latency, or any clock recovery circuits, which can increase energy consumption and overhead. In addition, the serial link design strategy can reduce resource consumption and the complexity of wire and pins to facilitate placement and routing. In this dissertation, a self-timed asynchronous circuit is used, which necessitates the usage of the pulse logic family. The link also includes the two-wire burst mode protocol. The time notion is included in the zero-line and one-line of the link, and the timing information is included in the transmitted pulse signal without the use of a clock.

The overall design process follows a hierarchical structure. Firstly, to achieve the logic function, the link is designed at the behavior level with VHDL code. The serializer and deserializer functions should therefore be performed at the transistor level. They are based on the pulse-logic library, which should be built initially. The transistors utilized in the design are all HVT transistors, which reduce current leakage and power consumption. The final step is to do timing characterization and optimization to ensure that the design works properly under various conditions. The entire point-to-point link can be built by using 28nm technology and can function at 5Gb/s with a power consumption of 0.5mW.

Autonomous vehicle (AV technology) relies heavily on vision based applications like object recognition, obstacle/collision avoidance etc. In order to achieve this, understanding and estimating the dynamics in the environment is extremely important. LIDARs are proven to detect both shape as well as the speed/movement of the objects in the scene but one of the biggest challenges faced in adapting LIDAR technology is the huge amount of data it produces and the way it is processed. Most of this data is redundant static information which results in wastage of system memory, computational resources, power and time. Inspired from biological retina, first Neuromorphic-Retina for LIDAR is proposed that is able to extract and encode movement happening at particular distance, particular angle and with particular velocity from raw LIDAR temporal pulses into unique spike sequences so that the information about the dynamic environment can be efficiently classified and processed by event based and low powered Neuromorphic processing unit. The system is designed in such a way that it avoids consumption of large amount of computational resources and system memory. Simulation results show that the Retina is able to filter out redundant static information from the LIDAR data stream thereby reducing data throughput of around 50 - 70 % with 5 - 22 % spatial quality loss (based on scenario) as well as remove noise caused due to luminous reflections. This has tremendous impact on system latency and power consumption due to drop in memory accesses.