N.P. van der Meijs

Book chapter (2)

Conference paper (1)

3 records found

Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations

Model order reduction of large RC circuits

Book chapter (2008) - N.P. van der Meijs (author)

Substrated resistance modeling by combination of BEM and FEM methodologies

Book chapter (2004) - E. Schrik (author) , N.P. van der Meijs (author)