A 0.1pJ freeze vernier time-to-digital converter in 65nm CMOS

Statistical transistor-Level Timing Analysis Using a Direct Random Differential Solver

Dynamic thermal estimation methodology for high performance 3D MPSoC

Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron

Considering crosstalk effects in statistical timing analysis

A CMOS 0.23pJ Freeze Vernier time-to-digital converter

Balanced Stochastic Truncation of Coupled 3D Interconnect

Adaptive thermal monitoring of deep-submicron CMOS VLSI circuits

New statistical timing analysis method considering process variations and crosstalk

Towards an intrinsically statistical SPICE-level simulator

A 11uW 0C-160 temperature sensor in 90 nm CMOS for adaptive thermal monitoring of VLSI circuits

An inspiring BSc-EE curriculum for science and engineering

Transistor-level gate model based statistical timing analysis considering correlations

Crosstalk-aware statistical interconnect delay calculation

Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method

A 3.72 ¿W Ultra-low power digital baseband for Wake-up Radios

Statistical Delay Calculation with Multiple Input Simultaneous Switching

Fast statistical analysis of RC nets subject to manufacturing variabilities

Fast Statistical analysis of RC Nets Subject tot Manufacturing Variabilities

Accuracy Consideration of a Non-Gaussian Interconnect Delay Model for Submicron CMOS Statistical Static Timing Analysis