N.P. van der Meijs

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Book chapter (2)

Conference paper (3)

5 records found

A 0.1pJ freeze vernier time-to-digital converter in 65nm CMOS

Conference paper (2014) - KL Blutman , J Angevare , A Zjajo , NP van der Meijs

A CMOS 0.23pJ Freeze Vernier time-to-digital converter

Conference paper (2013) - J Angevare , K Blutman , A Zjajo , NP van der Meijs

Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations

Conference paper (2010) - Q Tang , A Zjajo , MRCM Berkelaar , NP van der Meijs

Model order reduction of large RC circuits

Book chapter (2008) - NP van der Meijs

Substrated resistance modeling by combination of BEM and FEM methodologies

Book chapter (2004) - E Schrik , NP van der Meijs