Transformers are widely used in power electronics but their low operating frequency typically makes them bulky. Increasing the switching frequency can significantly reduce transformer size, weight, and production costs, which is particularly advantageous for portable applications such as chargers. This report investigates the operation of high-frequency transformers and presents the design and development of a working prototype operating at up to 3MHz.
Electrical parameters, including inductance, capacitance, and resistance, were measured using a Bode 100 vector network analyser (VNA) and validated through analytical models and finite element simulations in COMSOL Multiphysics. Based on these parameters, a transformer model was constructed using IEEE Std 390 [1] and verified in LTSpice against measured results. Toroidal cores made of soft ferrite materials in various sizes were evaluated, and round copper wire was initially used for windings. To minimize AC resistance at high frequencies, litz wire was selected for the final prototype. The completed transformer was integrated into a switching circuit operating at 1.5MHz, demonstrating successful high-frequency performance and practical viability.

This thesis presents the hardware development of the Qbead, an educational tool designed to make knowledge about quantum computing more accessible through a tangible representation of a qubit using a spherical LED display. The Qbead simulates the Bloch sphere, enabling users to visualize quantum states and gate operations in an interactive, physical format. The project focused on redesigning the Qbead’s hardware to address limitations in the previous version, including insufficient LED density, fragile PCB structure, and complex assembly. Key improvements include a newly designed flexible PCB with 107 LEDs arranged for more homogeneous coverage, a custom microcontroller shield integrating a 9-axis IMU and reducing soldering complexity, and an upgraded 3D-printed casing that improves structural integrity and simplifies assembly. These enhancements were validated through prototyping and testing, showing improved usability.

This thesis delves deeper into the design and implementation of a high-frequency DC to DC converter, focusing on the driving circuitry of a transformer based power conversion system operating at MHz frequencies. Because of more demand for smaller, lighter and more energy efficient designs, high-frequency transformers have become an interesting and promising alternative to the standard lower frequency topologies. The project investigates two different topologies, namely: a self oscillating circuit and a GaN based full-bridge inverter. Each of these accompanied by a rectifier stage.

The final prototype successfully operates at a frequency of at least 1 MHz, generating a sinusoidal waveform at the output of the transformer. The system also meet the requirements for achieving an efficiency of 80%, and design criteria such as load independence, compact size and a minimum input voltage of 50 V DC. However, the output power has not reached the desired level of 50 V at 2 A.

The project stresses the importance of precise timing and dead time control in high-frequency switching. While the self oscillating circuit showed promise in LTSpice simulations, it was not pursued due to its dependency on the load connected. Future work should be done to explore an improved component integration, and more advanced control strategies to reach the full 100 W output capability.

This thesis explores the development of the software framework for the Qbead. A physical representation of a quantum bit (qubit) designed to be held in the hand. Shaped as a sphere, the Qbead visualises the Bloch sphere from quantum mechanics, with internal LEDs that illuminate to display the qubit’s state. The main goal of the Qbead is to provide students with a more intuitive and accessible way to learn about quantum computing.

While the concept shows promise, the existing software framework lacks the necessary features to function as an effective educational tool. This project focuses on further developing the codebase to create a solid foundation for future use. By expanding the software and implementing quantum-related experiments, the Qbead can better support hands-on education in quantum mechanics.

The new classes are added to create a better framework for other functions. The X, Y, Z, and Hadamard single-qubit gates are implemented. 3 ways to detect input, rotating, shaking, and tapping have been added.
Some experiments are developed to show off the single-qubit gate functions and decoherence of the state.

As part of making a power grid simulator, a hardware controller is needed. This thesis specifically describes the design of such a controller. The objective is to design it in such a way that it is self-explanatory and interactive. Therefore, the following user controls and feedback are made possible. A small solar panel makes it possible to provide input for a solar generator in the simulation. A slider gives input for a wind farm in the simulation. This is visualized by adding a small physical turbine to the hardware, going faster or slower based on the input.
A small knob to go back or forward in the simulation, if pressed, pauses or resumes the time.
A RGB LED indicates the situation on the grid. Based on the loading of transmission lines, the color of the LED changes. These user-control actions and feedback from the simulation are processed on an Arduino Mega Rev3 development board. This uses an ATMega2560 microcontroller. To interact with the simulation, bidirectional serial communication is needed between the Arduino and the computer running the simulation with the Godot game engine. These components are implemented on a PCB to finalize the design.

This thesis describes the design and implementation of a LED Driving and Sensing Unit, one of the parts of a UV-C LED sterilization machine for the disinfection of plant seeds. The purpose of this part is to drive LEDs which can destroy different structures of pathogens. While doing this, certain parameters like temperature and ozone generation are being measured.
The report covers many design choices such as the choice to put the LEDs in arrays that are a combination of series and parallel circuits, or how SPI addressable variable resistors were used, in order to have full control over the LEDs and the sensing part. Furthermore, through a MATLAB script, it was discovered how the arrays of LEDs must be placed in specific manner to obtain a uniform radiation pattern. From this, it follows that using two arrays with radii of respectively 17 and 41 mm would work best. Furthermore, a literature research was done on UV-C and on what wavelength is theoretically the best for destroying pathogens on seeds. The focus was set on wavelengths of 255 nm and a combination of 275 nm and 285 nm. Also a 395 nm (UV-A) LED was used to investigate whether pathogens can be awakened from a hibernation state with the help of this type of light.
A boost converter capable of controlling the intensity of the LEDs by changing its gain with the aforementioned variable resistors was designed. Finally, the entire unit was tested successfully. The result of the research is a fully working LED driver module that can sense all parameters that need to be measured, completed with the design of a 3D CAD casing, which has all been manufactured and fabricated. This thesis does not include test results of the disinfection of plant seeds. This information will be included in the supplementary seed testing results report.

Highly accurate time sources, such as Cesium-based or GPS clocks, are the best candidates to provide a correct notion of time, but are too costly and impractical for implementation in every modern digital device. Ubiquitously, (crystal) oscillators are employed instead. To maintain a shared notion of time, the offsets and drift/jitter have to be compensated via the concept of synchronization, divided into time offset equalization and syntonization. Packet-based distribution protocols such as Network Time Protocol (NTP) and Precision Time Protocol (PTP) can provide time offset equalization, whilst synchronous Ethernet can deliver syntonization. To reach high synchronization accuracy, PTP and synchronous Ethernet can be combined into an improved protocol, referred to as White Rabbit. It enhances the one-way delay calculation through fine and coarse delay measurements. These improve PTP timestamps to reach sub-nanosecond synchronization accuracy.

The White Rabbit project has limitations though: it relies on extensive calibration parameter sets that are only available for limited devices and do not account for hardware variability. This is in contrast with the initial project objectives. Secondly, the update cycle of the hardware implementation is slow. Namely, the current White Rabbit switch is based on FPGA platforms from ten years ago. Thirdly, the switch contains costly components and requires full replacement of present network switches upon deployment.

This work opted to define a new switch design, which distributes the synchronization tasks over several smaller FPGAs to provide a low-cost implementation and improve applicability, whilst requiring minimal factory calibration and maintaining sub-nanosecond accuracy between devices.

The new switch concept is based on the smaller and widely applied White Rabbit node design. The proof of concept is based on two interconnected FPGAs forming a 1-port White Rabbit switch. Fine delay measurements, asymmetry estimations and fine delay compensations are applied to reach synchronization between the FPGAs. The Digital Dual Mixer Time Difference (DDMTD) is preferred for the fine delay measurements due to its superior resolution, area and invariance to large clock periods. A three-line asymmetry calculation is introduced and motivated to provide an improved one-way delay estimation. Lastly, the IDELAY element was selected to provide the fine delay compensation due to its process-voltage-temperature (PVT) invariance, negligible jitter addition and area demands.

Whilst both the fine delay measurement and fine delay compensation were thoroughly discussed by means of specifications and simulations, the three-line asymmetry calculation had to rely on a theoretical discussion. As such, measurements have shown that the transmission delay over an added bi-directional link is approximately equal when the clock signal moves from slave to master and vice versa. A large delay variability between other transmission lines is subsequently exposed. The variability leads to inaccurate one-way estimations with a traditional two-line approach. A three-line asymmetry calculation will be conclusively beneficial for the synchronization accuracy. The low-cost requirement of the distributed switch can be maintained through elimination of components in the slave and master node. The reduced switch lowers the hardware costs with approximately 25% by trading off cost-effectiveness with jitter filtering and consecutive performance.

Multiple voltage conversion ratio (VCR) recursive switched-capacitor (SC) DC-DC
converters, based on a number of basic 2:1 converters, are widely used for on-chip power supplies due to their flexible VCRs for higher energy efficiency. However, conventional multi-VCR SC converters usually have one or more 2:1 converters unused for some VCRs, which results in lower power density and chip area wastage. This paper presents a new recursive DC-DC converter system, which is able to dynamically reconfigure the connection of all on-chip 2:1 converter cells so that the unused converters in conventional designs can be re-used in this new architecture for increasing the load-driving capacity,
power density and power efficiency.

To validate the design, a 4-bit-input 15-ratio system was designed and fabricated in a 180-nm BCD process, which can support a maximum load current of 0.71mA and achieve a peak power efficiency of 93.1% with 105.3μA/mm^2 chip power density from a 2V input power supply. The measurement results show that the load-driving capacity can become 6.826×, 2.236× and 2.175× larger than the conventional topology when the VCR is 1/2, 1/4 and 3/4, respectively. In addition, the power efficiency under these specific VCRs can also be improved considerably.

Modern computing systems suffer due to inability of CMOS-device technology and conventional Von-Neumann architectures to support today's ever-increasing demand of high performance, reliability, cost and energy-efficiency. While CMOS device suffers from high static leakage, reduced reliability and manufacturing complexity; conventional computing architecture suffers from high power consumption with memory access and performance bottlenecks. Non-volatile and CMOS-compatible emerging memristive device technology with extremely compact memory structures offers in-memory computing solutions. However, research lacks quantitative benchmarking of memristor-based primitive logic designs. Moreover, the arithmetic and functional circuit design solutions are inefficient and hence incompetent to replace the state-of-the-art.The thesis first covers device level physics of different memristive devices, elaborating their basic structures, working principles and behavioural analyses using Verilog-A models. Building on single device behavioural analyses, a comprehensive exploration and quantitative benchmarking of all existing primitive gates is provided, thereby concluding that scouting logic design technique is the optimal logic gate to perform in-memory computing. Going forward, using scouting logic as the building block, the work presents efficient arithmetic and functional circuit designs that outperform previously proposed in-memory computing solutions and attempts to make a strong case to challenge the current CMOS-based state-of-the-art computing paradigm.Different flavours of a novel circuit design are proposed to tackle limitations common to circuits implementing primitive arithmetic operations and complex multiply-accumulate (dot-product) operations supporting data-intensive applications. The proposed circuit deploys in-built sample-and-hold and two bit-wise weighting techniques to enable pipelining and self-timing-path to improve accuracy against variations. As compared to 4-bit adder utilising integrate and fire circuit (IFC) that is optimised for area/power, the proposed design improves the speed, area, and energy consumption by 4X, 2.5X, and 11X, respectively. Incorporating additional components such as high-gain differential amplifier and modified IFC provides a highly accurate, linear, power efficient dot product engine with significant improvement in memristor endurance. To perform 64_4 dot 64_1, the proposed dot product engine improves the speed, area and energy consumption by 2X, 3.5X and 54X, respectively, as compared to area-efficient IFC-based engine, while also extending the range of operands operated in parallel by >3X. Compared to highly accurate SAR-ADC(current sense amplifier) based dot product engine, the proposed design improves the speed, area and energy by a factor of 0.4X(1.2X), 200X(6X) and 260X(108X), respectively, with comparable accuracy. Read endurance is significantly improved as < 0.1V is maintained across the memristors during the dot-product operation, as opposed to > 1V endured using prior proposed designs. To showcase the scalability and versatility of the proposed circuit designs, design prepositions of multi-operand 4-bit adder, 4x4 multiplier and 4-bit comparator are also presented. Supporting equations, graphs, figures and tables have been included to justify the choices made as part of this work and to enhance the understanding of novel non-volatile memristor based in-memory computing.