A 0.1pJ freeze vernier time-to-digital converter in 65nm CMOS
Conference Paper
(2014)
Author(s)
KL Blutman (External organisation)
J Angevare (External organisation)
A Zjajo (TU Delft - Electrical Engineering, Mathematics and Computer Science)
NP van der Meijs (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Research Group
Signal Processing Systems
DOI related publication
https://doi.org/10.1109/ISCAS.2014.6865071
Final published version
To reference this document use
https://resolver.tudelft.nl/uuid:2b4b194a-32bc-464f-8f05-3203ef5d0cbc
More Info
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Publication Year
2014
Language
English
Research Group
Signal Processing Systems
Pages (from-to)
85-88
Publisher
IEEE
ISBN (print)
978-1-4799-3431-7
Event
IEEE ISCAS 2014, Melbourne, Australia (2014-06-01 - 2014-06-05), Piscataway, NJ, USA
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