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Conference paper (2020) - Amir Zjajo
In this paper, we present neuromorphic system with built-in temporal control that allows the implementation of transient mechanisms and homeostatic regulation. Due to the interaction between conductance delay and plasticity rules, the network is forming a set of neuronal groups with time-locked, reproducible, and precise firing patterns. Experimental results obtained in 65 nm CMOS technology illustrate the feasibility of the methodology. ...
Conference paper (2019) - Amir Zjajo, Sumeet Kumar, Rene Van Leuken
Computation capability characteristics of neuromorphic analog/mixed-signal spiking neural networks offer capable platform for implementation of cognitive tasks on resource-limited embedded platforms. In this paper, we derive stochastic model of spiking neural processing systems for energy-efficient recognition and inference of biomedical systems. We examine imperfections in the network dynamics and noise-induced information processing, influence of the uncertainty on the behavior of the emulated networks, and impact on the clustering accuracy of cardiac arrhythmia. Experimental results indicate that stochasticity at networks connections is a adequate resource for deep learning machines. ...
Advanced driving assistance systems (ADAS) prepave regulators, consumers and corporations for the medium-term reality of autonomous driving with adaptive cruise control, collision avoidance and lane departure warning system. Various sensors like camera, RADAR and LIDAR, integrated into the vehicle assist driving. In addition, deep learning approaches are utilized in a wide range of applications ranging from object detection and scene segmentation to engine fault diagnosis and emission management to detect vehicle network intrusion. In this paper, we scope out the state of the art sensors subsystems in terms of its functionality, characteristics, specifications and communication protocol, and we describe cognitive deep learning based algorithms required for environment perception through these sensors. Subsequently, we analyze the cognitive algorithm by profiling the standard deep learning models, explore different compute platforms and possible algorithm and hardware optimization scenarios. ...
Conference paper (2019) - Amir Zjajo, Sumeet Kumar, Rene Van Leuken
In pulse-based neural networks, synaptic dynamics can have direct influence on learning of neural codes, and encoding of spatiotemporal spike patterns. In this paper, we propose an adaptive synapse circuit for increased flexibility and efficacy of signal processing units in neuromorphic structures. The synapse acts as a multi-layer computational network, and includes multi-compartment dendrites and different types of post-synaptic back propagating signals. With built-in temporal control mechanisms, the resulting reconfigurable network allows the implementation of synaptic homeostatics. ...

Biophysical Accuracy versus Hardware Complexity

Conference paper (2019) - Amir Zjajo
In this paper, we examine electro-chemically accurate, multi-compartment, neurosynaptic computational elements, and analyze their complexity, accuracy, and flexibility in signal processing of a time-varying task. We evaluate distributed patterns of simultaneously firing neurons in space and time, and we establish a transient synchrony and homeostatic regulation mechanism upon the underlying synaptic connectivity. With synchronic spiking, we form synchronous groups of neuronal subpopulations, which represent content forming a coherent entity. The neurosynaptic computational elements implemented on Xilinx Virtex 7 XC7VX550 FPGA board illustrate feasibility of the methodology. ...
Conference paper (2019) - Amir Zjajo, Sumeet Kumar, Rene Van Leuken
Energy-efficiency and computation capability characteristics of analog/mixed-signal spiking neural networks offer capable platform for implementation of cognitive tasks on resource-limited embedded platforms. However, inherent mismatch in analog devices severely influence accuracy and reliability of the computing system. In this paper, we devise efficient algorithm for extracting of heterogeneous activation functions of analog hardware neurons as a set of constraints in an off-line training and optimization process, and examine how compensation of the mismatch effects influence synchronicity and information processing capabilities of the system. ...
Journal article (2019) - Xuefei You, Amir Zjajo, Sumeet Kumar, Rene van Leuken
Synaptic dynamics is of great importance in realizing biophysically accurate neural behaviors and efficient synaptic learning in neuromorphic integrated circuits. In this paper, we propose a current-based synapse structure with multi-compartment receptors AMPA, NMDA and GABAa and a weight-dependent learning algorithm. The designed circuit offers distinctive dynamic features of receptors as well as a joint synaptic function. A cross-correlation methodology is applied to a two-layer RNN built by multi-compartment receptors to demonstrate the proposed synapse structure. An increased computation efficiency is verified through temporal synchrony detection among the neural layers in a noisy environment. The design implemented in TSMC 65 nm CMOS technology consumes 1.92, 3.36, 1.11 and 35.22 pJ per spike event of energy for AMPA, NMDA, GABAa and the advanced learning circuit, respectively. ...
Simulating large spiking neural networks with a high level of realism in a FPGA requires efficient network architectures that satisfy both the resource and interconnect constraints, as well as the changes in traffic patterns due to learning processes. In this paper, we propose a dataflow architecture based on a multipath ring topology that offers traffic shaping capabilities, and high energy-efficiency for the neuron-to-neuron communications. ...
Journal article (2018) - Amir Zjajjo, Jaco Hofmann, Gerrit Jan Christiaanse, Martijn van Eijk, Georgios Smaragdos, Christos Strydis, Carlo Galuzzi, Rene van Leuken, Alexander de Graaf
Simulation of brain neurons in real-time using biophysically meaningful models is a prerequisite for comprehensive understanding of how neurons process information and communicate with each other, in effect efficiently complementing in-vivo experiments. State-of-the-art neuron simulators are, however, capable of simulating at most few tens/hundreds of biophysically accurate neurons in real-time due to the exponential growth in the interneuron communication costs with the number of simulated neurons. In this paper, we propose a real-time, reconfigurable, multichip system architecture based on localized communication, which effectively reduces the communication cost to a linear growth. All parts of the system are generated automatically, based on the neuron connectivity scheme. Experimental results indicate that the proposed system architecture allows the capacity of over 3000 to 19 200 (depending on the connectivity scheme) biophysically accurate neurons over multiple chips. ...
The pathophysiological processes underlying the ECG tracing demonstrate significant heart rate and the morphological pattern variations, for different or in the same patient at diverse physical/temporal conditions. Within this framework, spiking neural networks (SNN) may be a compelling approach to ECG pattern classification based on the individual characteristics of each patient. In this paper, we study electrophysiological dynamics in the self-organizing map SNN when the coefficients of the neuronal connectivity matrix are random variables. We examine synchronicity and noise-induced information processing, influence of the uncertainty on the system signal-to-noise ratio, and impact on the clustering accuracy of cardiac arrhythmia. ...
Journal article (2017) - Sumeet S. Kumar, Amir Zjajo, Rene van Leuken
In this paper, we present the Immediate Neighbourhood Temperature (INT) routing algorithm which balances thermal profiles across dynamically-throttled 3D NoCs by adaptively routing interconnect traffic based on runtime temperature monitoring. INT avoids the overheads of system-wide temperature monitoring by relying on the heat transfer characteristics of 3D integrated circuits which enable temperature information from routers in the immediate neighbourhood to guide adaptive routing decisions. Experimental results indicate that INT yields balanced thermal profiles with upto 25% lower gradients than competing schemes, and shortens communication latencies by decreasing average network congestion by upto 50%, with negligible overheads. ...
Conference paper (2017) - Amir Zjajo, Sumeet Kumar, Rene van Leuken
In this paper, we propose a reconfigurable neural spike classifier based on neuromorphic event-based networks that can be directly interfaced to neural signal conditioning and quantization circuits. The classifier is set as a heterogeneity based, multi-layer computational network to offer wide flexibility in the implementation of plastic and metaplastic interactions, and to increase efficacy in neural signal processing. Built-in temporal control mechanisms allow the implementation of homeostatic regulation in the resulting network. The results obtained in a 90 nm CMOS technology show that an efficient neural spike data classification can be obtained with a low power (9.4 μW/core) and compact (0.54 mm2 per core) structure. ...

Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors

Journal article (2017) - Sumeet S. Kumar, Amir Zjajo, Rene van Leuken
This paper investigates the challenges of dark silicon that impede the performance and reliability of 3-D stacked multiprocessors. It presents a multipronged approach toward addressing the thermal issues arising from high-density integration in die stacks, spanning architectural techniques, design methodologies, and runtime temperature management. Importantly, this paper provides novel insights into the causes of hotspot formation in 3-D ICs and details a practical approach toward exploring and mitigating performance-limiting thermal behavior early in the system design flow. ...
In a neuromorphic integrated circuit synaptic dynamics are of great importance to capture accurate neural behaviors. In this paper, we propose a current-based synapse design mediated with multiple receptor types, namely AMPA, NMDA and GABAa, and a weight-dependent learning algorithm. Due to various biological conducting mechanisms, the receptors demonstrate different kinetics in response to stimulus. The designed circuit offers distinctive features of receptors as well as the joint synaptic function. An increased computation ability is verified through synchrony detection in a two-layer recurrent network of synapse clusters. The design implemented in TSMC 65 nm CMOS technology consumes 1.92, 3.36, 1.11 and 35.22 pJ per spike event of energy for AMPA, NMDA, GABAa receptors and the advanced learning circuit, respectively. ...
Conference paper (2017) - Haipeng Lin, Amir Zjajo, Rene van Leuken
The high level of realism of spiking neuron networks and their complexity require a substantial computational resources limiting the size of the realized networks. Consequently, the main challenge in building complex and biologically-accurate spiking neuron network is largely set by the high computational and data transfer demands. In this paper, we implement several efficient models of the spiking neurons with characteristics such as axon conduction delays and spike timing-dependent plasticity. Experimental results indicate that the proposed real-time data-flow learning network architecture allows the capacity of over 2800 (depending on the model complexity) biophysically accurate neurons in a single FPGA device. ...
Conference paper (2016) - A. Zjajo, Santosh Astigimath, R. van Leuken
In this paper, we propose a time-based, programmable-gain A/D converter allowing for an easily-scalable, and power-efficient, implantable, biomedical recording system. The converter circuit is realized in a 90 nm CMOS technology, operates at 640 kS/s, occupy an area of 0.022 mm2, and consumes less than 2.7 μW corresponding to a figure of merit of 6.2 fJ/conversion-step. ...
Conference paper (2016) - A. Zjajo, R. van Leuken
Robust, power- and area-efficient spike classifier, capable of accurate identification of the neural spikes even for low SNR, is a prerequisite for the real-time, implantable, closed-loop brain-machine interface. In this paper, we propose an easily-scalable, 128-channel, programmable, neural spike classifier based on nonlinear energy operator spike detection, and a boosted cascade, multiclass kernel support vector machine classification. The power-efficient classification is obtained with a combination of the algorithm and circuit techniques. The classifier implemented in a 65 nm CMOS technology consumes less than 41 μW of power, and occupy an area of 2.64 mm2. ...
Conference paper (2016) - A. Zjajo, R. van Leuken
In this paper, we present a neural recording interface circuit for biomedical implantable devices, which includes low-noise signal amplification, band-pass filtering, and current-mode successive approximation A/D signal conversion. The integrated interface circuit is realized in a 65 nm CMOS technology, and consumes less than 2.1 μW/channel of which A/D converter consumes 367 nW, corresponding to a figure of merit of 14 fJ/conv.-step, while operating from a 1 V supply. ...
Journal article (2016) - A. Zjajo
The nature of the neural signals, increasing density in multichannel arrays, information quality, and feasible data bandwidth pose significant challenges encountered in a power-efficient design of implantable brain-machine interface. In this paper, we propose a set of solutions to address this design problem at both circuit- and system abstraction level. In particular, we review circuits for real time read-out of neural signals and discuss the role of classification in hardware neural processing architectures; we review the challenges of realizing power-efficient circuits in physical systems and present examples of mixed-signal electronic circuits that implement them; we provide a broad view of optimization approaches, and their possible combination in effective complimentary techniques. We validate the approach with experimental results obtained from our own circuits and systems, and argue how the circuits and systems presented in this work represent a valid set of components for power-efficient design of implantable multichannel brain-machine interface. ...
Conference paper (2016) - G.J. Christiaanse, A. Zjajo, C. Galuzzi, R. van Leuken
For comprehensive understanding of how neurons communicate with each other, new tools need to be developed that can accurately mimic the behaviour of such neurons and neuron networks under `real-time' constraints. In this paper, we propose an easily customisable, highly pipelined, neuron network design, which executes optimally scheduled floating-point operations for maximal amount of biophysically plausible neurons per FPGA family type. To reduce the required amount of resources without adverse effect on the calculation latency, a single exponent instance is used for multiple neuron calculation operations. Experimental results indicate that the proposed network design allows the simulation of up to 1188 neurons on Virtex7 (XC7VX550T) device in brain real-time yielding a speed-up of x12.4 compared to the state-of-the art. ...