Transistor-level gate modeling for Nano CMOS circuit verification considering statistical process variations
Conference Paper
(2010)
Author(s)
Q Tang (TU Delft - Signal Processing Systems)
A Zjajo (TU Delft - Signal Processing Systems)
MRCM Berkelaar (TU Delft - Signal Processing Systems)
NP van der Meijs (TU Delft - Signal Processing Systems)
Research Group
Signal Processing Systems
To reference this document use:
https://resolver.tudelft.nl/uuid:248646d2-790b-4682-904b-df3725108ac1
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Publication Year
2010
Language
English
Research Group
Signal Processing Systems
Pages (from-to)
1-10
Publisher
Springer
ISBN (print)
978-3-642-17751-4
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