A Highly Concurrent, Memory-Efficient AER Architecture for Neuro-Synaptic Spike Routing

Master thesis (2019)

Authors

J.P. Coenen Electrical Engineering, Mathematics and Computer Science

Contributors

T.G.R.M. van Leuken Signal Processing Systems - EEMCS (supervisor 1)
Z. Al-Ars Computer Engineering - EEMCS (supervisor 2)
S.S. Kumar Signal Processing Systems - EEMCS (coach)
Amir Zjajo Signal Processing Systems - EEMCS (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2019 Joris Coenen
More Info
expand_more

Published Date

17-04-2019

Language

English

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

One of the challenges of neuromorphic computing is efficiently routing spikes from neurons to their connected synapses. The aim of this thesis is to design a spike-routing architecture for flexible connections on single-chip neuromorphic systems. A model for estimating area, power consumption, memory, spike latency and link utilisation for neuromorphic spike-routing architecture is described. This model leads to the proposal for a new spike-routing architecture with a hybrid addressing scheme and a novel synaptic encoding scheme. The proposed architecture is implemented in a SystemC simulation tool with a supporting tool for encoding arbitrary SNN topologies for the synapse encoding scheme. Running the simulations with synthetic benchmarks and a handwriting recognition SNN shows that the proposed architecture is memory-efficient and provides low latency spike-routing with high synaptic activation concurrency.