On-chip Self Timed SNN Custom Digital Interconnect System
J. Huang (TU Delft - Electrical Engineering, Mathematics and Computer Science)
T.G.R.M. van Leuken – Mentor (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Aditya Dalakoti – Graduation committee member (Innatera Nanosystems B.V)
C. Galuzzi – Coach (TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
A Spiking neural network (SNN) is a type of artificial neural network which encodes information using spike timing, network structure, and synaptic weights to emulate the information processing function of the human brain. Within an SNN, it is always required to support the spike transmission that travels between neurons(array). This thesis aims to design a customized high-speed interconnect system which supports multi-point communication in a neuromorphic computing system. The burst-mode two-wire protocol in point-to-point communication is applied in this interconnect system, which is designed in high-level modelling with SystemC. In order to improve the utilization of hardware resources, a virtual channel system is involved. Furthermore, this system could be extended to a variable number of neuron arrays to support different types of spiking neural networks. Also, optimization methods are adopted to increase the transmission rate of the system and save unnecessary energy consumption. The interconnect system could achieve a throughput of 3.802 Gbits/s with the given MNIST use case, based on the evaluation of simulation results.