Advanced automotive vehicles are based on the real-time fusion of an increasing number of automotive sensors. For precise fusion of different sensors, measurements need to be synchronized both temporally and spatially. This thesis aims to design a hardware temporal synchronization block as part of the PRISTINE systolic array accelerator project for multi-sensor data fusion. In this process, we study and address several temporal sensor synchronization issues that are characteristic of the considered system as well as any other typical sensor fusion system. First and foremost, we handle the problem of estimating the actual time of sensor measurement by exploring well-known filtering techniques such as Kalman, mean and median filters. A suitable filter is selected for implementation based on the statistical characteristics of the observed sensor cycle times, the complexity of the filters and the quality of obtained estimates. Next, we address the issue of reconstructing incoming sensor data streams according to the estimated sensor measurement times while maintaining minimal latency and synchronization error by employing an adaptive stream buffering technique utilized in distributed multimedia systems. An analysis of the effects of the stream synchronization algorithm's parameters on buffering latency and synchronization error was presented. Finally, the above synchronization solution was efficiently implemented on hardware by making certain modifications and design decisions to the algorithm. A method to evaluate the whole temporal synchronization process is proposed and the obtained results on real sensor data are presented.

Convolutional Neural Networks (CNN) have become a popular solution for computer vision problems. However, due to the high data volumes and intensive computation involved in CNNs, deploying CNNs on low-power hardware systems is still challenging.
The power consumption of CNNs can be prohibitive in the most common implementation platforms: CPUs and GPUs. Therefore, hardware accelerators that can exploit CNN parallelism and methods to reduce the computation burden or memory requirements are still hot research topics. Quantization is one of these methods. One suitable quantization strategy for low-power deployments is logarithmic quantization.

Logarithmic quantization for Convolutional Neural Networks (CNN): a) fits well typical weights and activation distributions, and b) allows the replacement of the multiplication operation by a shift operation that can be implemented with fewer hardware resources.
In this thesis, a new quantization method named Jumping Log Quantization (JLQ) is proposed. The key idea of JLQ is to extend the quantization range, by adding a coefficient parameter "s" in the power of two exponents ($2^{sx+i}$).

This quantization strategy skips some values from the standard logarithmic quantization. In addition, a small hardware-friendly optimization called weight de-zeroing is proposed in this work. Zero-valued weights that cannot be performed by a single shift operation are all replaced with logarithmic weights to reduce hardware resources with little accuracy loss.

To implement the Multiply-And-Accumulate (MAC) operation (needed to compute convolutions) when the weights are JLQ-ed and de-zeroed, a new Processing Element (PE) have been developed. This new PE uses a modified barrel shifter that can efficiently avoid the skipped values.
Resource utilization, area, and power consumption of the new PE standing alone are reported. Resource utilization and power consumption in a systolic-array-based accelerator are also reported.
The results show that JLQ performs better than other state-of-the-art logarithmic quantization methods when the bit width of the operands becomes very small.

Hardware cryptographic algorithm implementation is easy to attack by side-channel attacks. The power-based side-channel attacks are powerful among several side-channel attacks. This attack methods use the relationship between the leakage model and power traces to reveal the secret key. Some existing countermeasures like mask and hide can protect the algorithms from attacking. However, they can not break the relationship between power traces and the leakage model. Based on the property of the neural network, the linear relationship can be easily broken. Furthermore, the spiking neural network is more hardware-friendly than a conventional neural network. The design replaces the sbox in AES with a pipeline spiking neural network-based sbox and implements it in hardware. The help of the FPGA attack platform demonstrates that the proposed design can resist DPA, CPA, Template Attacks, and Deep Learning-based attacks.The developed model is focused on the design phase of the New Sluices and it showed the impact of scope change on the project progress. The simulations resulted in 19 months of delay compared to the initial duration of the project. Moreover, it was shown that the impact of the second order effect contributed within 10 months of that delay. Finally, two further investigations were conducted regarding staff morale and optimism bias. The results showed that uncertainties and poor risk management can impact the staff morale through rework, lack of transparency, and bad leadership. To overcome the loss of morale the presence of a skilled manager and implementing an effective risk management system, where all the different types of project risks are incorporated is essential. Regarding the optimism bias research, it was shown that optimism bias influenced the decision-making process in the project. It was hypothesized that it resulted from the ‘Accumulation of Planning Fallacy’ that was happening during the iterations of the planning process. The proposed solution for overcoming optimism bias was the usage of the ‘outside view’, when forecasting the costs, durations, and benefits of the projects. ‘Outside view’ would bypass optimism bias and produce more accurate predictions.

The recently introduced posit number system was designed as a replacement for IEEE 754 floating point, to alleviate some of its shortcomings. As the number distribution of posits is similar to the data distributions in deep neural networks (DNNs), posits offer a good alternative to fixed point numbers in DNNs: using posits can result in high inference accuracy while using low precision numbers. The number accuracy is most important for the first and last network layers to achieve good performance. For this reason, these are often computed using larger precision fixed point numbers compared to the hidden network layers. Instead, these can be computed using low precision posit, to reduce the memory access energy consumption and the required memory bandwidth. The hidden layer computation can still be performed using cheaper fixed point numbers.
An inference accuracy analysis is performed to quantify what the effect of this approach is on the VGG16 network for the ImageNet image classification task. Using 8 bit posit for the first and last network layer instead of 16 bit fixed point is shown to result in a top-5 accuracy degradation of only 0.24%. The hidden layers are computed using 8 bit fixed point in both cases.
The design of a parameterized systolic array accelerator performing exact accumulation is proposed that can be used in a scale-out system along with fixed point systolic array tiles. To increase hardware utilization, a hybrid posit decoder is designed to enable fixed point computation on the posit hardware. Using this hardware, the entire network can be computed using 8 bit data, instead of using 16 bits for some layers. This reduces energy consumption and the complexity of the memory hierarchy.