Floating-G_m-based current sensors are effective in rejecting PWM common-mode voltage. But their linearity drops at high voltages due to substrate-current-induced body effect in LDMOS devices. To address this issue, this work introduces a DLL-assisted dynamic body biasing sensor in 0.18μm BCD, improving HD2 by 31dB and THD+N by 14dB. And a peak THD+N of -82.3dB is achieved in the meanwhile. It supports 60V common-mode, rejects PWM up to 2MHz, and enables high-linearity sensing for high power audio and motor-driver systems.

This article presents a photovoltaic energy harvester (PVEH) that achieves high maximum power point tracking (MPPT) efficiency and power conversion efficiency across a 100 000× input power dynamic range (DR) (from 10 µW to 1 W). Wide-dynamic-range operation is challenging due to the inherent tradeoff between MPPT accuracy and controller power consumption. To address this, an adaptive power-scalable MPPT scheme is proposed, employing a direct power-to-digital converter (PDC) that eliminates the need for current sensing, analog multipliers, or lookup tables (LUTs). The PDC utilizes an equivalent power comparison technique, minimizing its power consumption. The MPPT controller autonomously scales its power, consuming minimal energy in low-irradiation conditions while maintaining high tracking accuracy and speed in high-irradiation conditions. Furthermore, a multiple-counting technique mitigates comparator noise and settling errors. Implemented in a 180-nm CMOS process, the harvester achieves a peak MPPT efficiency of 99.9% and maintains >98% across the entire range, representing a 10× improvement in DR over prior art. It also achieves a competitive power conversion efficiency of >82% (peak of 92%) over the same DR.

This paper presents a photovoltaic energy harvesting (PVEH) system achieving both high Maximum Power Point Tracking (MPPT) efficiency (η _MPPT) and power conversion efficiency (η _CONV) across a wide input power dynamic range (DR), employing a direct input power-to-digital converter (PDC) and an adaptive power-scalable MPPT scheme. The proposed PVEH achieves >98% (with a peak of 99.9%) η _MPPT across a 100,000 × DR (10 μ W to 1 W), representing a 10 × improvement over the state-of-the-art, as well as a competitive η _CONV of >82% (with a peak of 92%) across the same DR.

Capacitive touch screens have become the dominant user interface over the past decade. Achieving high framerates with low power consumption remains a critical design goal for touch systems. The conventional charge-recycling technique reduces driving power by 64%, but it relies on off-chip capacitors. To address this issue, we propose a tri-level energy recycling scheme, in which energy released during the 2-to-1 transition is recycled to power the 0-to-1 transition on the complementary channel. This approach achieves a 25% power reduction using on-chip transmission gates. Additionally, a compressive sensing method is introduced to selectively process touched RX channels while bypassing the others, reducing the number of fine ADCs by a factor of four compared to conventional two-step sensing. The proposed techniques are implemented in a 65 nm CMOS process and integrated into a 32×20 channel prototype occupying 2.4 mm². Measurement results show that the chip consumes only 2.6 mW at a framerate of 1513 Hz. The signal-to-noise ratio (SNR) reaches 49.7 dB for finger touch and 28.7 dB for a 1 mm Φ stylus, resulting in an energy efficiency of 10.66 pJ/step.

The dynamic range (DR) of digital-input closed-loop class-D amplifiers (CDAs) is typically limited by the noise introduced by their resistive DAC (RDAC) or current-steering DAC (IDAC). It could be improved by using tri-level cells in the IDAC, but this has not yet been realized in high-voltage (HV) CDAs due to the large difference in the common-mode levels between the DAC and the CDA. This article describes an HV CDA directly driven by an HV IDAC. By using the same output common mode for the digital-to-analog converter (DAC) and CDA, the noise penalty associated with shifting the common mode is avoided. To address the distortion due to mismatch and intersymbol interference (ISI) in the IDAC, a transition-rate-balanced bidirectional real-time dynamic element matching (RTDEM) technique is also introduced. Fabricated in a 180-nm BCD process, the CDA prototype achieves a DR of 121.7 dB and a peak THD+N of -104.0 and -109.0 dB for 1- and 6-kHz inputs, respectively. It can deliver a maximum of 14 W into an 8-Ω load with a power efficiency of 90%.

This article presents a hybrid magnetic current sensor for contactless current measurement. Pick-up coils and Hall plates are employed to sense the high and low-frequency fields, respectively, generated by a current-carrying conductor. Due to the differentiating characteristic of the pick-up coils, a flat frequency response can then be obtained by summing the outputs of the coil and the Hall paths and passing the result through a 1st-order low-pass filter (LPF). For maximum resolution, the LPF corner frequency (2 kHz) is set such that the noise contribution of each path is equal. To suppress the coil-path offset without the use of large ac coupling capacitors, an area-efficient dual dc servo loop (D3SL) is used. This effectively suppresses the coil-path offset, resulting in a total offset of 73 μT , which is mainly dominated by the Hall path. Fabricated in a standard 0.18-μm CMOS process, the current sensor occupies 3.9 mm2 and draws 7.1 mA from a 1.8 V supply. It achieves 43 mA resolution in a 5 MHz bandwidth, which is 1.5 × better than the state-of-the-art hybrid sensors. It also achieves the lowest energy efficiency FoM (3.5 ×) among CMOS magnetic current sensors.

Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digital-input CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak textTHD+N of about -98textdB [2], [3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, lSI, and intermodulation distortion. A prototype implemented in a 0.18mum BCD process achieves 120.9dB DR and -111.2textdB peak textTHD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Omega/4Omega load with a 90%/86% efficiency.

This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between the chopping, pulsewidth modulation (PWM), and DAC sampling frequency is analyzed to avoid negative impacts on the DR and linearity. Real-time dynamic element matching (RTDEM) is employed to address distortion due to mismatch in the DAC, while its intersymbol interference (ISI) is eliminated by deadbanding. The prototype, implemented in a 180-nm bipolar, CMOS, and DMOS (BCD) process, achieves 120.9 dB of DR and a peak total harmonic distortion plus noise (THD+N) of-111.2 dB. It can drive a maximum of 15/26 W into an 8-/4-Ω load with a peak efficiency of 90%/86%.

This paper presents a Class-D piezoelectric speaker driver that employs a quadrature feedback chopping scheme (QCS). Compared to a conventional single feedback chopping scheme (SCS), the use of QCS can eliminate the timing skew between low-voltage (LV) and high-voltage (HV) choppers, greatly improving large-signal linearity. A prototype implemented in a 180nm BCD process achieves a peak THD+N of 88dB/-92.5dB for a 1kHz/6kHz input frequency and 37μ VR MS output noise (A-weighted) while driving a 4μ F load. Thanks to QCS, the large-signal THD+N has been improved by 29 dB, while the output voltage swing achieving -60dB THD+N has been extended from 86.9% to 99.5% of the full-scale (FS).

Magnetic current sensors are widely used in applications where galvanic isolation and wide bandwidth (BW) are desired, such as in switched-mode power supplies and motor drivers. By using Hall plates for low frequencies and pick-up coils for high frequencies, hybrid magnetic sensors can achieve high resolution (tens of textmA) over a wide frequency range (up to 15MHz) [1]-[3]. However, previous designs exhibit either poor gain flatness over frequency or limited energy efficiency. This work presents a hybrid magnetic current sensor that textachievespm 1. 1% gain flatness, which is 3times better than prior art [1]-[3]. Its energy efficiency is also 11times better than the state-of-the-art [1], [4], [5].

This article presents a hybrid magnetic current sensor for galvanically isolated measurements. It consists of a CMOS chip that senses the magnetic field generated by current flowing through a lead-frame-based current rail. Hall plates and coils are used to sense low-frequency (dc to 10 kHz) and high-frequency (10 kHz to 5 MHz) magnetic fields, respectively. With the help of on- chip calibration coils, the biasing current of the Hall plates is trimmed to match the sensitivity of the Hall and coil signal paths. The sensitivity drift of the coil path with temperature is compensated by using temperature-dependent gain-setting resistors, while the drift of the Hall path is compensated by biasing the Hall plates with a proportional- to-absolute-temperature (PTAT) current. The resulting sensitivity drift is less than 9% from-40 °C to 80 °C. The offset of the Hall plates is reduced by the current spinning technique, and the resulting ripple is suppressed by a multiplexed ripple-reduction loop (MMRL). Fabricated in a standard 0.18-μm CMOS process, the current sensor occupies 4.6 mm2 and draws 7.8 mA from a 1.8-V supply. It achieves a gain variation of only ±2% in a 5-MHz BW. It also achieves high energy efficiency, with an figure of merit (FoM) of 1.6 fW/Hz.

This article presents a class-D amplifier (CDA) with high dynamic range (DR). To eliminate the typically dominant noise contribution of a resistive feedback network, the input and feedback signals are chopped and applied to a capacitive feedback network. However, this leads to high-voltage (HV) transients at the input of the loop filter, which, due to timing and impedance mismatch in the chopped feedback network, could degrade linearity and even overstress low-voltage (LV) core devices. Robust processing of the HV chopped feedback signal is guaranteed with chopper timing skew correction, chopper impedance matching, and deadbanding. The prototype, implemented in a 180-nm bipolar-CMOS-DMOS (BCD) process, achieves 121.4 dB of DR, 5.9 dB higher than state-of-the-art closed-loop CDAs, and 8-μVRMS output-referred noise (A-weighted). It also achieves a peak total harmonic distortion (THD) + N of -109.8 dB and a peak efficiency of 93%/88% while driving 15 W/26 W into an 8-4-Ω load.

Class-D audio amplifiers produce electromagnetic interference (EMI), which often needs to be suppressed by an external LC filter. However, due to component nonlinearity, this filter can itself cause significant distortion. This article presents a class-D amplifier that suppresses LC filter nonlinearity by 49 dB and is robust to ±30% variations in its cutoff frequency. This is achieved by a dual-loop architecture, in which an inner loop provides stability, while an outer loop provides the high gain needed to suppress the LC filter and output-stage nonlinearity. A prototype, implemented in a 180-nm BCD process, achieves -121.5-dB total harmonic distortion (THD) and -107.1-dB THD+N, which is maintained to within 3 dB even as the LC filter cutoff frequency is varied from 62 to 106 kHz. It can deliver a maximum of 21 W into a 4-Ω load with 87% efficiency and 12 W into an 8-Ω load with 91% efficiency, measured at 10% THD.

Class-D amplifiers (CDAs) are often used in audio applications due to their superior power efficiency. Due to the sensitivity of the human ear, a large dynamic range (DR) is desired, and audio DACs with up to 130dB DR are commercially available [1]. However, the DR of the CDAs they drive is typically much lower [2]-[4], mainly due to the thermal noise introduced by the input resistors of their resistive feedback networks. Reducing this resistance is difficult, as it reduces the CDA's input impedance and increases the required loop-filter capacitance. Alternatively, the CDA could be configured as a capacitively coupled chopper amplifier (CCCA), whose capacitive feedback network could then achieve low noise without reducing input impedance. However, the large PWM component present at its output would then saturate its input stage. By exploiting the inherent PWM filtering present in a feedback-after-LC architecture, this paper presents a capacitively coupled chopper CDA, resulting in significantly improved DR and THD+N. The prototype achieves 8V_RMS of integrated output noise (A-weighted), a 121.4dB DR, and -1 09.8dB THD+N while delivering a maximum of 15/26W into an 8/4Omega load with 93%/88% efficiency.

The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of -109.1 dB and can deliver a maximum of 14 W into an 8- \Omega load with 93% efficiency while occupying a silicon area of 5 mm2.