This article presents a cost-effective, fully integrated shunt-resistor-based in-line current sensor that delivers high linearity and strong PWM rejection, enabling precise current measurement and control in dynamic driving systems like robotics, imaging, and audio. To mitigate the self-heating of the on-chip shunt resistor, which degrades linearity, a location-based thermal compensation technique is proposed. This technique reduces self-heating-induced distortion, improving THD+N by up to 23.6 dB over the full operating range without calibration. In addition, a floating transconductance (FG_m) stage is introduced to reject the high dv/dt, high-voltage PWM components at the switching node of the power stage, enabling robust current sensing with this PWM common mode voltage. The prototype is implemented in a 180 nm BCD process and demonstrates a peak THD+N of–87.2 dB and a dynamic range (DR) of 89.1 dB. It achieves up to 2 MHz, 14.4 V PWM rejection with 2 V/ns dv/dt, and supports a ±6 A bidirectional current range.

This article presents a photovoltaic energy harvester (PVEH) that achieves high maximum power point tracking (MPPT) efficiency and power conversion efficiency across a 100 000× input power dynamic range (DR) (from 10 µW to 1 W). Wide-dynamic-range operation is challenging due to the inherent tradeoff between MPPT accuracy and controller power consumption. To address this, an adaptive power-scalable MPPT scheme is proposed, employing a direct power-to-digital converter (PDC) that eliminates the need for current sensing, analog multipliers, or lookup tables (LUTs). The PDC utilizes an equivalent power comparison technique, minimizing its power consumption. The MPPT controller autonomously scales its power, consuming minimal energy in low-irradiation conditions while maintaining high tracking accuracy and speed in high-irradiation conditions. Furthermore, a multiple-counting technique mitigates comparator noise and settling errors. Implemented in a 180-nm CMOS process, the harvester achieves a peak MPPT efficiency of 99.9% and maintains >98% across the entire range, representing a 10× improvement in DR over prior art. It also achieves a competitive power conversion efficiency of >82% (peak of 92%) over the same DR.

This paper presents a photovoltaic energy harvesting (PVEH) system achieving both high Maximum Power Point Tracking (MPPT) efficiency (η _MPPT) and power conversion efficiency (η _CONV) across a wide input power dynamic range (DR), employing a direct input power-to-digital converter (PDC) and an adaptive power-scalable MPPT scheme. The proposed PVEH achieves >98% (with a peak of 99.9%) η _MPPT across a 100,000 × DR (10 μ W to 1 W), representing a 10 × improvement over the state-of-the-art, as well as a competitive η _CONV of >82% (with a peak of 92%) across the same DR.

This paper presents a sub-1V delta-sigma modulator (DSM) with power and bandwidth (BW) scalability for IoT applications. It is built around a fully dynamic and low-voltage floating inverter amplifier (LVFIA). To extend the power and BW scalability of the LVFIA, its relatively supply-independent bias current is auto-controlled by DSM's sampling frequency f_s. Dynamic techniques such as auto-zeroing and chopping are applied to achieve low noise. Fabricated in a 130nm CMOS, the proposed sub-1V DSM shows a near-consistent SNDR (90dB) and linearly scalable power and BW (2.5nW/Hz) over a ×30 scaling range of f_s. It achieves Walden FoM and Schreier FoM of 51.3fJ/conv-step and 175.7dB, respectively.

Capacitive touch screens have become the dominant user interface over the past decade. Achieving high framerates with low power consumption remains a critical design goal for touch systems. The conventional charge-recycling technique reduces driving power by 64%, but it relies on off-chip capacitors. To address this issue, we propose a tri-level energy recycling scheme, in which energy released during the 2-to-1 transition is recycled to power the 0-to-1 transition on the complementary channel. This approach achieves a 25% power reduction using on-chip transmission gates. Additionally, a compressive sensing method is introduced to selectively process touched RX channels while bypassing the others, reducing the number of fine ADCs by a factor of four compared to conventional two-step sensing. The proposed techniques are implemented in a 65 nm CMOS process and integrated into a 32×20 channel prototype occupying 2.4 mm². Measurement results show that the chip consumes only 2.6 mW at a framerate of 1513 Hz. The signal-to-noise ratio (SNR) reaches 49.7 dB for finger touch and 28.7 dB for a 1 mm Φ stylus, resulting in an energy efficiency of 10.66 pJ/step.