Vds current sensing has the potential to improve power density, efficiency, and cost compared to conventional current sensing methods by removing the need for a dedicated (quasi-)lossy sensing device. However, achieving high precision requires a temperature compensation method that has traditionally come at the expense of flexibility, test cost, or power density. This work proposes an online calibration method based on small signal resistance measurement through the periodic injection of small submicrosecond current pulses that are orthogonal to the load current. This provides an estimate of the large signal resistance that is insensitive to manufacturing tolerance and device type. Furthermore, junction temperature can be simultaneously estimated from the resistance variation. With 129mW injection power, the method achieves 0.54A RMS single point calibrated current error over a ±54A range on a 48V single phase experimental platform. Since all circuitry is connected parallel to the power stage, the method is suited to integration into a smart gate driver IC.

This thesis describes the analysis, design, prototype implementation, and measurement results of high-performance Class-D amplifiers (CDAs) for audio applications.

This thesis describes the development of high-performance Class-D audio amplifiers, outlining their significance in modern audio systems. The primary aim is to reduce the system cost and size associated around Class-D amplifiers by minimizing the use of off-chip components, while ensuring high performance and audio fidelity.

Chapter 1 introduces audio amplifiers as integrated circuits, highlighting their role in amplifying electrical signals to drive loudspeakers in various applications. It outlines the key factors influencing amplifier design, including system cost and size, output power, efficiency, electromagnetic interference (EMI), and audio fidelity. The chapter briefly discusses two major classes of amplifiers- Class-AB and Class-D amplifiers (CDAs), particularly emphasizing the latter for high efficiency benefits on account of the switching output stage. Additionally, it introduces the two types of speakers that the amplifiers in this work are optimized to drive, the conventional electrodynamic speaker and the increasingly popular piezoelectric speaker. The discussion includes the advantages and disadvantages of each speaker type and how their electrical impedances impact amplifier design.

Chapter 2 delves into the architectural and circuit techniques used in modern CDAs, comparing different output stage topologies and modulation schemes, and their impact on high-frequency PWM energy and ripple current — key measures of the amplifier’s EMI performance. It introduces conventional AD / BD PWM modulation schemes, highlighting their high frequency PWM characteristics from DM and CM perspectives, before exploring more complicated multi-level and multi-phase architectures that aim to reduce the ripple content and EMI. The trade-offs between these modulation schemes in terms of EMI performance and component requirements are examined. It discusses the benefits of increasing the PWM switching frequency above the AM band ( 1.7MHz), which then allows for smaller and cheaper LC filters. Pulse-density modulation (PDM) using a 1-bit delta-sigma modulator (ΔΣM) is covered, emphasizing its benefits in terms of linearity and challenges related to wideband quantization noise and EMI. Lastly, the chapter also addresses the adaptability of CDAs for driving various speaker loads, particularly newer piezoelectric speakers, and discusses innovative techniques for damping LC resonance without external resistors, significantly reducing power consumption and system cost.

Chapter 3 outlines the development of a 28WCDA for automotive applications, employing a hybrid multibit ΔΣM-PWM scheme to achieve high linearity and low EMI in the AM band. The design features a fully-differential 3rd order loop filter, a multilevel non-uniform quantizer, and an H-bridge output stage that operates at a switching frequency above the AM band. This hybrid modulation technique addresses the limitations of 1-bit delta-sigma modulation, and significantly reducing out-of-band emissions while maintaining high linearity across a broad output power range thanks to the high-gain loop filter. The digital and analog circuits in this design, including the loop filter integrators and quantizer, are designed with low-voltage devices to ensure area and power efficiency. In contrast, the high-power output stage and driving circuits are built with more robust high-voltage devices. This prototype amplifier meets the stringent CISPR-25 EMI standards within the AM band using a relaxed LC filter, while also achieving high linearity, dynamic range, and supply rejection. Chapter 4 introduces a CDA that incorporates a dual voltage/current feedback (VFB/ CFB) topology, specifically designed to drive capacitive piezoelectric speaker loads without the need for external damping resistors. This dual-loop structure effectively mimics a series resistor in an LCR network, allowing for resistor-less LC resonance damping, thereby reducing cost, size, and power consumption. Load current sensing, used in the CFB path, is implemented using purely low-side on-chip sense resistors, thereby avoiding high-frequency switching issues and simplifying the readout network. This low-side sensing is feasible due to the push-pull modulation scheme, which is advantageous for a low-power design. Techniques such as CFB filtering and chopping are employed to reduce non-idealities like noise and non-linearity in the feedback paths. The prototype, fabricated in a 180 nm BCD process, can drive a 4 μF load with a peak current of 4.4 A and achieves an idle power consumption of 122 mW. Measurement results confirm the system’s efficacy in damping LC resonance and maintaining high performance, with significant power savings compared to traditional designs using external resistors.

Chapter 5 builds upon the dual feedback architecture introduced in Chapter 4 by incorporating a quadrature chopping scheme to further enhance the linearity and noise performance of Class-D amplifiers. This technique addresses timing skew issues between low-voltage input choppers and high-voltage output choppers, which can degrade signal linearity and increase noise. The quadrature chopping scheme dynamically matches the timing of the choppers, resulting in significant improvements in large-signal total harmonic distortion (THD) and a reduction in noise foldback into the audio band. The chapter presents measurement results that demonstrate the extension in the linear output of the amplifier to close to 95% the full-scale.

Chapter 6 concludes the thesis by summarizing the key findings and contributions of the research. It highlights the original contributions, including the hybrid PWM-DSM modulation scheme, the dual feedback topology for resistor-less damping of capacitive piezoelectric speaker loads, and the quadrature chopping scheme for further improved linearity and noise performance. The chapter also discusses potential future research directions, such as further optimization of EMI performance through advanced modulation techniques, improved current sensing methods, and enhanced feedback accuracy.

Class-D amplifiers have gained significant importance in automotive applications due to its high efficiency. However, to meet strict electromagnetic interference (EMI) requirements, an LC filter is necessary, which, unfortunately, introduces nonlinearity to the system. This project proposes an architecture by implementing a dual voltage/current feedback loop to suppress the nonlinearity of the LC filter. The voltage feedback is put after the LC filter to suppress its nonlinearity. The current feedback splits the complex poles from the LC filter to stabilize the system.
By implementing current feedback as the inner loop, this design achieves a significant reduction in the LC filter’s bulk and cost in comparison to state-of-the-art, while maintaining a good total harmonic distortion (THD) level of around -110 dB. This architecture is also robust to +/-30% variations in LC filter cut-off frequency. The chip is fabricated using a 180-nm BCD process, with a die size of 3 mm × 2.28 mm.

DC-to-DC converters have been used in portable electronic applications such as laptops and mobile phones where power efficiency is very important. In these applications, basic converters like buck and boost converters are used. However, the conversion ratio of conventional boost converters is not high. To achieve a high conversion ratio, the duty cycle of the conventional boost converters must be increased drastically, which increases the conduction loss. This thesis presents a topology to tackle this issue. A control system is designed and the pulse frequency modulation (PFM) method is used. In this thesis, a complete analysis of this topology, such as efficiency evaluation and stability analysis, is provided. This circuit is designed in 180nm BCD technology. Simulation results show it has a wide load range (0 to1.8A), high line regulation 0.8%/V, load regulation 2.9%/A, while achieving 88.1%, 93.0%, and 94.8% when CR = 5, CR = 4.5, and CR = 3.7, at <\ba= 1.2A respectively.

AC-coupled amplifiers (ACCA) offer lower noise than traditional resistor feedback amplifiers, which benefits signal-to-noise ratio (SNR) for audio applications. Due to the DC isolation of the capacitor, a feedback resistor is needed to set the virtual ground of ACCA’s amplifier. However, an external feedback resistor raises system noise and transforms the ACCA into a high-pass filter, impacting the audio bandwidth signal (20- 20kHz). A GΩ resistor can shift the cut-off frequency outside the audio bandwidth while reducing noise. Various high-resistance resistor structures have been applied in biomedical readout integrated circuits (ICs), such as sequence detection, ECG, and EEG signal readout. However, the achieved signal-to-noise ratio and total harmonic distortion (THD) are unsuitable for audio applications. This thesis discusses different methods of making high-resistance resistors, such as duty-cycled resistors, switchedcapacitor resistors, and pseudo resistors, exploring their possibility in audio applications. This work proposes an active current reducer structure with an equivalent resistance of 200GΩ (± 20%) and an output RMS noise of 2.1μV for ACCA. This circuit is built in the 180-nm BCD process achieving -106 dB to -116 dB THD and 96.7 dB SNR. Index Terms – audio amplifier, high-resistance resistors, duty-cycled resistor, switchedcapacitor resistor, pseudo resistor, active current reducers, total harmonic distortion (THD). 

Class D amplifiers (CDA) have been used considerably in audio applications due to their high-efficiency behavior. Compared to standalone analog input CDAs, digital input CDAs are less sensitive to electromagnetic interference (EMI), which is preferred in automotive applications. For digital input CDAs, multi-bit current-steering DACs using tri-level units offer high dynamic range (DR) compared with other types of DAC. The main challenge in designing low total harmonic distortion plus noise (THD+N) and high DR IDAC lies in noise, mismatch, and ISI reduction. In this project, a new ISI resilient dynamic element matching technique is developed for mismatch shaping and ISI reduction in IDAC.

Class-D amplifiers have gained popularity for their high-power efficiency, exceeding 90%. Among them, digital-input Class-D amplifiers stand out due to their superior integration and increased immunity to electromagnetic interference (EMI). This project introduces a high-performance digital-input Class-D amplifier, aiming for a dynamic range larger than 130 dB while maintaining total harmonic distortion (THD) at approximately -110 dB.

It employs a capacitive digital-to-analog converter (CDAC) to minimize noise. Mismatch in the CDAC is addressed through mismatch shaping techniques. Additionally, an open-loop transconductance stage is incorporated into the loop filter, enhancing dynamic range and striving for optimal performance. Extra paths are introduced in the loop filter to guarantee that amplifier swings are maintained within the designated range.

GaN transistors have advantages over conventional Si MOSFETs, such as lower on-resistance, lower parasitic capacitance, higher break-down voltage, etc. However, due to the lack of the body diode, when GaN transistors conduct reverse current during dead time, the source-drain voltage (VSD) can be very large (up to 4-5 V, depending on the output current). High reverse conduction voltage leads to large power loss during dead time for the GaN class D amplifier. In this project, a dead time control circuit is proposed. With the dead time control circuit, the dead time can be reduced from a large default value to around 5 ns. The output power of the class D amplifier can be improved, and the third-order harmonic distortion can also be improved by 5-10 dB for different corners and temperatures.

Optical sensor has been widely used in daily life. One of the important applications of optical sensors is the ambient light sensor installed in portable devices. The screen brightness of portable devices like smartphones is designed to be automatically adjusted based on the ambient environment. The ambient light detection is realized using optical devices like Photodiode (PD), where the incident light is converted into an analog current. The induced PD current is measured by a readout circuit so that the output of the readout circuit controls the screen brightness accordingly.
This thesis presents an energy-efficient current-mode optical sensor readout circuit that achieves a wide dynamic range. Hourglass ADC is used as the core structure of the readout circuit, applying current-to-frequency conversion. The output of the readout is the digital count within 100ms conversion time. The dark counts of the designed PD readout circuit are less than three counts. The noise count is less than one when output counts are smaller than 100 and less than 1% when output counts are more than 100. Fabricated in a 0.18μm CMOS process, the readout circuit achieves a 160dB dynamic measurement range comparable to the prior-of-art. The entire circuit consumes power of0.113mW and occupies a chip area of 0.056mm2.

Class D audio amplifier is widely used in many electronic applications such as automobiles, laptops, and mobile phones. However, electromagnetic interference (EMI) generated by Class-D audio amplifiers frequently requires an external LC filter for suppression. The LC filter itself causes significant nonlinearity. Hence, feedback after LC is widely used to suppress this nonlinearity. Nevertheless, component tolerance in practical LC components causes instability problems in the feedback-after-LC Class-D amplifier. This thesis presents a class-D amplifier that suppresses LC filter nonlinearity by 40 dB at least and calibrates the variation of the cut-off frequency (f_LC) of the LC filter between 70kHz and 200kHz. This is implemented in a differential architecture, where the inner loop and outer loop ensure high in-band loop gain and stability, and the unity gain frequency is calibrated by a variable gain amplifier (VGA). This circuit is built in the 180-nm BCD process, achieving -108dB~-126dB total harmonic distortion (THD) after compensating for different LC cut-off frequencies.

Class-D amplifiers are quickly becoming the standard in many audio applications. Their highly efficient behavior and wide power range make these amplifiers more suitable than traditional Class A/AB audio amplifiers. Battery-powered devices are a particularly interesting sub-field due to their special demand for extended battery duration and higher efficiency. An output power lower than 2 W, along with good performances in terms of linearity and efficiency, is often required. Many stand-alone Class-D Amplifiers have analog inputs, making them susceptible to interference that negatively impacts their behavior. This problem can be mitigated by employing an insensitive input digital interface. Many standard solutions often require complex architectures, which limit these systems' reliability. This work proposes a digital-input class-D amplifier with a multi-level output stage that, together with a relatively low (480 kHz) switching frequency, reduces idle power consumption while achieving good linearity. Based on a 180 nm BCD technology, it can drive a 16-Ω load showing pre-layout simulated performances: -111.3 dB THD+N, 115.6 DR, 91.4 % peak efficiency, and 2.14 mW idle power consumption.

Class-D amplifiers are widely used in audio applications that require a high power efficiency. A high PSRR is beneficial when the power supply contains significant audio band content. Due to mismatches present in the feedback, these can dominate the PSRR of the class-D amplifier, provided the amplifier has sufficient loop gain. No literature has been found that describes a solution to improving the PSRR and CMRR across the full audio band. This work proposes chopping of the input and feedback resistors in a class-D to address this issue. With this technique's application, a >100dB PSRR and CMRR across the audio band is achieved.

Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. State-of-the-art imaging systems demand the detection of small amounts of charge with small time-resolution and limited power consumption, creating an implementation dead-end for the typical readout topology. In this thesis, a particle detection readout based on an intersymbol interference cancellation scheme is introduced to address this issue. Evaluated in post-layout simulations, the proposed architecture can detect generated charge as small as 160 aC with 97.8 % certainty. The readout can operate with event-rates up to 400 MEvent/s while only consuming
2.85 mW of power.

Fruit-frost during spring is one of the main causes of damage to the harvest of fruit in orchards. Various systems using different methods of preventing spring-frost are available on the market. To determine when these systems should be activated, the temperature in the orchard needs to be determined. In this project, a self-sustaining autonomous temperature sensor network is designed, which is capable of making a 3D temperature map of the orchard. The system is used to warn farmers when the threat of fruit-frost occurs and to gather data on the spatial variation of the temperature in the orchard. In this thesis, the focus is put on designing the smart measurement and control system. This includes choosing an appropriate control unit and temperature sensors. Also, the software for the control unit is designed, which allows for a smart measurement scheme that balances energy usage and measurement frequency. Finally, an estimation of the energy usage of the subsystem is given based on theoretical analysis.

Many countries in the world face the problem of fruit frost during spring, which results in the loss of harvested crops. Solutions exist to prevent the fruit to freeze, however this requires that the temperature is known. Therefore, a smart autonomous temperature sensor network is designed that is capable of acquiring a 3D temperature profile of a fruit orchard to detect fruit frost. This thesis discusses the design of the energy harvesting and control module, which is one of the three sub-modules of the system. The goal is to sustain the energy demands of the sensor in a durable way, in order to operate for 20 years without requiring maintenance. To achieve this, several ambient energy sources and their harvesting techniques are investigated and simulated to examine the energy that can be harvested. This resulted in the use of solar energy, harvested by a solar cell and controlled by a maximum power point tracking module. Next, different energy storage implementations are considered to store the harvested energy temporarily. The use of a 5 F supercapacitor is concluded. Furthermore, an energy monitoring circuit is designed to measure the energy stored in the supercapacitor. Full system reliability simulations are done to verify the complete design by utilising the solar irradiance and temperature data of the past ten years. From these simulations is concluded that the design can sustain the energy demands of the sensor at all times.

In this thesis, the design and implementation of a wireless communication module and an accompanying network are discussed. This wireless communication module is used in a device which communicates frost temperatures measured at orchards. The goal is to gather data on how fruit frost develops on orchards, and to warn a fruit farmer if it starts freezing. First, several wireless communication protocols are discussed and the one best suited for the application is chosen. It is decided to use the LoRaWAN communication protocol. Then, the off-the-shelf hardware components which are required to implement the LoRaWAN communication protocol are chosen. Furthermore, LoRa communication parameters and the LoRaWAN network structure are discussed. A scheduling system is designed and proposed to increase the reliability of the network. At last, network simulations are performed to verify the chosen implementation.

Soil water-content sensors based on the measurement of soil impedance are widely used for the detection of rain-fall induced slope failure and other agriculture applications. In principle, low-leakage sensors can measure soil water content down to 4%, but they require readout systems capable of generating soil excitation signals at frequencies ranging from 1KHz to 1MHz. However, existing commercial products do not cover this frequency range. To solve this problem, a new readout system is proposed in this thesis. By using sinusoidal excitation, implemented by a pulse-width- modulated driver, and synchronous detection, the readout system achieves less than 1% measurement error from 1KHz to 1MHz.

Digital isolators are devices that connect one electrical system block to another over a galvanically isolating barrier. They allow electrical systems to communicate with each other even though they may operate at vastly different potentials. They also do the job of eliminating potentially damaging ground loops between the two systems. This thesis presents a digital isolator based on inductive coupling. It presents a better alternative to the traditional approach of using optocouplers. The design employs a transmitter and a receiver which communicates digital signals over an isolation barrier with emphasis on low power and high common-mode rejection. The design achieves a common-mode transient immunity of 100kV/us, a data rate of 50Mbps, power consumption of 2mA per channel and signal delay less than 15ns.

Voltage references are one of the fundamental building blocks for designing any analog processing circuit. It serves as a reference for Analog to Digital Converters (ADCs), Digital to Analog Converters (DACs), power/voltage regulators and other measurement and control circuits. The performance of all these circuits cannot be better than the performance of the reference. Hence, it is very important that the voltage reference is very robust and performs reliably under process, supply, temperature or noise variations (PVT & N). Today, with the development of scalable quantum computing, there is a need for such a reference operating at cryogenic temperatures. Currently, the state of the art quantum circuits operates at ∼20 mK. To process and control the information flow, to and from these quantum processors, one requires an analog circuit to operate as close as possible to the quantum circuit, so as to make the full system scalable and more reliable since no line interconnect to room-temperature electronics would be required. As a step towards that idea, it is desired to push the operating temperature of the classical circuits as low as 4 K where enough cooling power is available without disturbing the operation of the quantum circuit. One of the basic blocks to be shifted to cryogenic temperatures is the voltage reference circuit. This thesis presents a systematic design of such a cryogenic voltage reference block, taking into account the device and circuit performance at 4 K. The targeted specifications are comparable to the references designed for standard industrial temperature range (233 K to 400 K). However, it is designed to work over an extremely wide temperature range (4 K to 400 K) to understand how far one can stretch the circuits designed with conventional CMOS. Two different variants of references are presented with the simulated performance of both over the industrial temperature range. A novel approach towards higher-order compensation is also presented which is expected to perform better than conventional CMOS reference over a wide range. To test their performance over the entire operating range (4 K to 400 K) and verify the designs, a tape-out is planned for October 2019.