This thesis presents the design of a low-power digital-input Class-D amplifier for battery-powered headphone applications. This Class-D amplifier operates with pulse density modulation (PDM) at a 12.288 MHz sampling frequency with three-level and dynamic hysteresis operation in the power stage to enhance the efficiency across a wide output power range. A three-level resistive digital-to-analog converter (RDAC) with reset-then open control strategy is used to improve the dynamic range while maintaining good linearity. This design is implemented in 16 nm FinFET technology. With a 1.8 V supply and a 40-Ω + 4-mH speaker load, the Class-D amplifier achieves a dynamic range (DR) of 116.7 dB and an idle power consumption of 1.71 mW. At the 23 mW maximum output power, it achieves 88.7% efficiency and a peak total harmonic distortion (THD) of -105.7 dB.