Superconducting nanowire single-photon detectors (SNSPDs) have emerged as leading cryogenic photon detectors, thanks to their high detection efficiency and low jitter. However, their large-scale integration remains limited by the wiring bottleneck between the cryogenic detectors and their room-temperature readout electronics. In applications such as color-center-based quantum computers (QCs), thousands of detectors may need to operate in parallel within a limited cryogenic cooling budget, thus asking for a scalable, low-power cryogenic electronic readout. To address these needs, this work introduces a cryogenic readout circuit directly wire-bonded to the SNSPD and using a high-impedance input to maximize the quality of the detector signal, thus relaxing the requirement of the cascaded amplifier and reducing its power consumption. An active quenching circuit is then adopted to ensure a reliable reset after the latching of the detector induced by such high input impedance. Implemented in 40-nm CMOS with an active area of <0.14 mm², the system achieves competitive performance at 0.1 K, delivering low timing jitter (<40 ps), high speed (dead time of ≈5 ns), and dark count rates (DCRs) below 1 Hz, while achieving a 5× reduction in power consumption (down to 20 μW) with respect to the cryogenic-readout state-of-the-art. Its ultralow-power operation and compact footprint make the proposed solution well-suited for integration within large-scale quantum-computing architectures.

This work presents a cryo-CMOS smart temperature sensor operating from room temperature down to 5 K. By adopting sensing elements (CMOS bulk diodes, pMOS/DTMOS in weak inversion) that circumvent the poor cryogenic performance of Si BJTs, a robust switched-capacitor second-order sigma–delta readout and cryogenic-aware design techniques, the sensor achieves a maximum error of ±0.73 K (four samples and two-point trim), a resolution below 0.05 K for a 102.4-ms readout duration, and a power consumption of 15.5 µW 93.5 µW) at 5 K (296 K).

The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of dc bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this article presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryogenic CMOS (cryo-CMOS) demultiplexer and a cryo-CMOS dc digital-to-analog converter (DAC) have been developed in a 22-nm fin field-effect transistor process to control a codeveloped 2-D array designed with 648 single-hole transistors. Thanks to the dissipation below 120 µ W, the whole system operates at temperatures below 70 mK in a custom-built electrical/mechanical infrastructure embedded in a standard single-pulse-tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold structures, allowing to store 96 unique bias voltages over a 3 V range with a voltage drift between 60 µ V / s and 18 mV/s. This work demonstrates a tight integration at mK temperatures of cryo-CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors toward the large number of qubits required for a practical quantum computer.

Increasing demand for cryogenic electronics aimed at quantum sensors and computing technologies asks for accurate and quantifiable calibration methods and techniques. In this work, we present a structured approach to generate the nominal RF responses of standard artifacts, enabling wideband vector network analyzer (VNA) calibration algorithms, i.e., short, open, load, and reciprocal (SOLR), at cryogenic temperatures. Moreover, we present an EM simulation strategy to generate the perturbations in the artifacts’ responses based on mechanical fabrication tolerances and calculate an equivalent RF response uncertainty. Both the nominal and perturbed standard responses are computed at (user defined) cryogenic temperatures, by combining thermo-mechanical responses with the electromagnetic solver. A circuit simulator-based measurement model (MM) is used to compute the uncertainties of the cryogenic setups used in this work. Error contributions arising from the propagation of VNA noise, switch nonidealities, calibration artifacts uncertainties, temperature fluctuations, and temperature gradient over the interconnects are included in the MM. For validation, measured results of a coaxial air transmission line at 77 K and 4.2 K are presented and compared with 3-D EM simulation predictions. Finally, the measurement uncertainties are detailed in a budget analysis describing the individual contributions.

This paper presents a scalable cryogenic readout solution for Superconducting Nanowire Single-Photon Detectors (SNSPDs) tailored for the readout of color-center-based qubits. The readout circuit, wire-bonded directly to the SNSPD, utilizes high input impedance to boost the signal amplitude, hence reducing the power consumption, and active quenching to prevent the latching induced by the high impedance. Fabricated in 40-nm CMOS in a 0.14-mm ² active area, the proposed system demonstrates competitive performance at 0.1 K, featuring low jitter [<60 ps Full Width at Half Maximum (FWHM)], high speed (dead time ≈ 5 ns) and low dark count rate (<1 Hz), while dissipating only 20 μ W. Such an ultra-low power and compact area enables the readout integration within a large-scale colorcenter quantum computer.

Quantum computers require large-scale error correction codes to circumvent the limited fidelity of physical qubits. However, current error decoders are either not scalable to practical code sizes or cannot meet the strict real-time decoding requirements. This work presents a novel decoder for stabilizer error correction codes that exploits hyperdimensional computing to offer an efficient hardware implementation for large-scale codes, thus achieving low latency and high throughput. Next to a universal approach for generating the necessary hypervectors, an efficient method specific to surface codes is devised. In this very first implementation, the proposed decoder outclasses popular graph-based decoders for small surface codes with depolarizing noise and efficiently scales to large codes, thus representing both a suitable solution for near-term real-time error correction and a promising alternative for future large-scale codes.

This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2 K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.

This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in weak inversion to achieve continuous operation from room temperature (RT) down to cryogenic temperatures. Their accuracy limitations due to curvature, body effect, and mismatch are investigated and experimentally validated. Implemented in 40-nm CMOS, the references show a line regulation better than 2.7%/V from a supply as low as 0.99 V. By applying dynamic element matching (DEM) techniques, a spread of 1.2% (3σ ) from 4.2 to 300 K can be achieved, resulting in a temperature coefficient (TC) of 111 ppm/K. As the first significant statistical characterization extending down to cryogenic temperatures, the results demonstrate the ability of the proposed architectures to work under cryogenic harsh environments, such as space- and quantum-computing applications.

We realize high-fidelity gates for the two-qubit system formed by NV center. Using gate set tomography, we report gate fidelities exceeding 99%, and analyze the origin of the errors.

The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-threshold-voltage (LVT) DRAM at 4.2 K is up to 2 × more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 ,000 × , thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This article introduces a theoretical framework to evaluate the effect of various parameters, such as the readout probe power, readout chain's noise performance, and integration time on the intrinsic readout signal-to-noise ratio, and thus readout fidelity of RF gate-based readout systems. By analyzing the underlying physics of spin qubits during readout, this work proposes a qubit readout model that takes into account the qubit's quantum mechanical properties, providing a way to evaluate the tradeoffs among the aforementioned parameters. The validity of the proposed model is evaluated by comparing the simulation and experimental results. The proposed analytical approach, the developed model, and the experimental results enable designers to optimize the entire readout chain effectively, thus leading to a faster, lower power readout system with integrated cryogenic electronics.