Micromagnet-enabled electric-dipole spin resonance (EDSR) is an established method for high-fidelity single-spin control in silicon, although so far experiments have been restricted to one-dimensional arrays. In contrast, qubit control based on hopping spins has recently emerged as a compelling alternative, with high-fidelity baseband control realized in sparse two-dimensional hole arrays in germanium. In this work, we commission a ²⁸Si/SiGe 2 × 2 quantum dot array both as a four-qubit device using EDSR and as a two-qubit device using baseband hopping control. We establish a lower bound on the fidelity of the hopping gate of 99.50(6)%, which is similar to the average fidelity of the resonant gate. The hopping gate also circumvents the transient pulse-induced resonance shift from heating observed during EDSR operation. To motivate hopping spins as an attractive means of scaling silicon spin-qubit arrays, we propose an extensible nanomagnet design that enables engineered baseband control of large spin arrays.

Semiconductor spin qubits have emerged as a promising platform for quantum computing, following a significant improvement in their control fidelities over recent years. Increasing the qubit count remains challenging, beginning with the fabrication of small features and complex fan-outs. A particular challenge has been formed by the need for individual barrier gates to control the exchange interaction between adjacent spin qubits. Here, we propose a method to vary two-qubit interactions without applying pulses on individual barrier gates while also remaining insensitive to detuning noise in first order. Experimentally we find that changing plunger gate voltages over 300 mV can tune the exchange energy J from 100 kHz to 60 MHz. This allows us to perform two-qubit operations without changing the barrier gate voltage. Based on these findings we conceptualize a spin qubit architecture without individual barrier gates, simplifying the fabrication while maintaining the control necessary for universal quantum computation.

The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of dc bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this article presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryogenic CMOS (cryo-CMOS) demultiplexer and a cryo-CMOS dc digital-to-analog converter (DAC) have been developed in a 22-nm fin field-effect transistor process to control a codeveloped 2-D array designed with 648 single-hole transistors. Thanks to the dissipation below 120 µ W, the whole system operates at temperatures below 70 mK in a custom-built electrical/mechanical infrastructure embedded in a standard single-pulse-tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold structures, allowing to store 96 unique bias voltages over a 3 V range with a voltage drift between 60 µ V / s and 18 mV/s. This work demonstrates a tight integration at mK temperatures of cryo-CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors toward the large number of qubits required for a practical quantum computer.

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 10⁵ cm² V⁻¹ s⁻¹ and low percolation density of 6.9(1) × 10¹⁰ cm⁻². These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz^−1/2 and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.

The efficient control of a large number of qubits is one of the most challenging aspects for practical quantum computing. Current approaches in solid-state quantum technology are based on brute-force methods, where each and every qubit requires at least one unique control line—an approach that will become unsustainable when scaling to the required millions of qubits. Here, inspired by random-access architectures in classical electronics, we introduce the shared control of semiconductor quantum dots to efficiently operate a two-dimensional crossbar array in planar germanium. We tune the entire array, comprising 16 quantum dots, to the few-hole regime. We then confine an odd number of holes in each site to isolate an unpaired spin per dot. Moving forward, we demonstrate on a vertical and a horizontal double quantum dot a method for the selective control of the interdot coupling and achieve a tunnel coupling tunability over more than 10 GHz. The operation of a quantum electronic device with fewer control terminals than tunable experimental parameters represents a compelling step forward in the construction of scalable quantum technology.

The small footprint of semiconductor qubits is favorable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in the gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2 × 2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.

Semiconductor spin qubits have gained increasing attention as a possible platform to host a fault-tolerant quantum computer. First demonstrations of spin qubit arrays have been shown in a wide variety of semiconductor materials. The highest performance for spin qubit logic has been realized in silicon, but scaling silicon quantum dot arrays in two dimensions has proven to be challenging. By taking advantage of high-quality heterostructures and carefully designed gate patterns, we are able to form a tunnel coupled 2 × 2 quantum dot array in a ²⁸Si/SiGe heterostructure. We are able to load a single electron in all four quantum dots, thus reaching the (1,1,1,1) charge state. Furthermore, we characterize and control the tunnel coupling between all pairs of dots by measuring polarization lines over a wide range of barrier gate voltages. Tunnel couplings can be tuned from about 30 μ eV up to approximately 400 μ eV . These experiments provide insightful information on how to design 2D quantum dot arrays and constitute a first step toward the operation of spin qubits in ²⁸Si/SiGe quantum dots in two dimensions.

Highly uniform quantum systems are essential for the practical implementation of scalable quantum processors. While quantum dot spin qubits based on semiconductor technology are a promising platform for large-scale quantum computing, their small size makes them particularly sensitive to their local environment. Here, we present a method to electrically obtain a high degree of uniformity in the intrinsic potential landscape using hysteretic shifts of the gate voltage characteristics. We demonstrate the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts that then remain stable at least for hours. Applying our method, we homogenize the pinch-off voltages of the plunger gates in a linear array for four quantum dots, reducing the spread in pinch-off voltages by one order of magnitude. This work provides a new tool for the tuning of quantum dot devices and offers new perspectives for the implementation of scalable spin qubit arrays.