The computational power and fault tolerance of future large-scale quantum processors derive in large part from the connectivity between the qubits. One approach to increase connectivity is to engineer qubit–qubit interactions at a distance. Alternatively, the connectivity can be increased by physically displacing the qubits. For semiconductor spin qubits, several studies have investigated spin coherent shuttling of individual electrons, but high-fidelity transport over extended distances remains to be demonstrated. Here we report shuttling of an electron inside an isotopically purified Si/SiGe heterostructure using electric gate potentials. In a first set of experiments, we form static quantum dots and study how spin coherence decays during bucket-brigade shuttling, where we repeatedly move a single electron between up to five dots. Next, for conveyor-mode shuttling, we create a travelling-wave potential, formed with either one or two sets of sine waves, to transport an electron in a moving quantum dot. This method shows a spin coherence an order of magnitude better than the bucket-brigade shuttling. It allows us to displace an electron over an effective distance of 10 μm in under 200 ns while preserving the spin state with a fidelity of 99.5% on average. These results will guide future efforts to realize large-scale semiconductor quantum processors, making use of electron shuttling both within and between qubit arrays.

The design and benchmarking of quantum computer architectures traditionally rely on practical hardware restrictions, such as gate fidelities, control, and cooling. At the theoretical and software levels, numerous approaches have been proposed for benchmarking quantum devices, ranging from, inter alia, quantum volume to randomized benchmarking. In this work, we utilize the quantum information-theoretic properties of multipartite maximally entangled quantum states, in addition to their correspondence with quantum error-correction codes, permitting us to quantify the entanglement generated on near-term bilinear spin-qubit architectures. For this aim, we introduce four metrics that ascertain the quality of genuine multipartite quantum entanglement, along with circuit-level fidelity measures. As part of the task of executing a quantum circuit on a device, we devise simulations, which combine expected hardware characteristics of spin-qubit devices with appropriate compilation techniques; we then analyze three different architectural choices of varying lattice sizes for bilinear arrays, under three increasingly realistic noise models. We find that if the use of a compiler is assumed, sparsely connected spin-qubit lattices can approach comparable values of our metrics to those of the most highly connected device architecture. Even more surprisingly, by incorporating crosstalk into our last noise model, we find that, as error rates for crosstalk approach realistic values, the benefits of utilizing a bilinear array with advanced connectivity vanish. Our results highlight the limitations of adding local connectivity to near-term spin-qubit devices, and can be readily adapted to other qubit technologies. The framework developed here can be used for analyzing quantum entanglement on a device before fabrication, informing experimentalists on concomitant realistic expectations.

Micromagnet-enabled electric-dipole spin resonance (EDSR) is an established method for high-fidelity single-spin control in silicon, although so far experiments have been restricted to one-dimensional arrays. In contrast, qubit control based on hopping spins has recently emerged as a compelling alternative, with high-fidelity baseband control realized in sparse two-dimensional hole arrays in germanium. In this work, we commission a ²⁸Si/SiGe 2 × 2 quantum dot array both as a four-qubit device using EDSR and as a two-qubit device using baseband hopping control. We establish a lower bound on the fidelity of the hopping gate of 99.50(6)%, which is similar to the average fidelity of the resonant gate. The hopping gate also circumvents the transient pulse-induced resonance shift from heating observed during EDSR operation. To motivate hopping spins as an attractive means of scaling silicon spin-qubit arrays, we propose an extensible nanomagnet design that enables engineered baseband control of large spin arrays.

This paper presents extensive guidelines for the design of an integrated DC-readout interface for semiconductor spin qubits. Since the focus is on the readout via a single electron transistor (SET), the SET behavior and performance are first described and modeled, showing that the signal-to-noise ratio (SNR) theoretically achievable by a SET-based DC-readout is significantly beyond the state-of-the-art. Practical circuit architectures for implementing a DC-readout, such as the voltage amplifier, the transimpedance amplifier, the charge sampling, and the current pre-amplifier, are then analyzed by deriving their design equations and trade-offs. As a result, the practical performances of those different solutions are evaluated and compared, thus presenting clear selection criteria for the readout architecture and its design equations given the specific parameters of the SET sensor.

Direct multiqubit gates are becoming critical to facilitate quantum computations in near-term devices by reducing the gate counts and circuit depth. Here, we demonstrate that fast and high-fidelity three-qubit gates can be realized in a single step by leveraging small anisotropic and chiral three-qubit interactions. These ingredients naturally arise in state-of-the-art spin-based quantum hardware through a combination of spin-orbit interactions and orbital magnetic fields. These interactions resolve the key synchronization issues inherent in protocols relying solely on two-qubit couplings, which significantly limit gate fidelity. We confirm with numerical simulations that our single-step three-qubit gate can outperform existing protocols, potentially achieving infidelity ≤ 10⁻⁴ in 80–100 ns under current experimental conditions. To further benchmark its performance, we also propose an alternative composite three-qubit gate sequence based on anisotropic two-qubit interactions with built-in echo sequence and show that the single-step protocol can outperform it, making it highly suitable for near-term quantum processors.

Continuous rounds of quantum error correction (QEC) are essential to achieve faulttolerant quantum computers (QCs). In each QEC cycle, thousands of ancilla quantum bits (qubits) must be read out faster than the qubits' decoherence time (<<T2∗~120μs for spin qubits). To address this urgent need, several CMOS receivers operating at cryogenic temperatures (cryo-CMOS RXs) have recently been introduced for gate-based [1] and RF reflectometry [2] readout of spin qubits, as well as transmons' dispersive readout [3]. However, they have a few shortcomings. First, due to the temperatureindependent shot noise of transistors in nanometer CMOS technology [4], their measured noise temperature (TN) is limited to 40K, thus degrading qubit readout fidelity. Second, due to their large TN, prior art showed either only the electrical performance of their chips by applying a relatively large (i.e., -85dBm [2]) modulated signal directly to the RX input [2,3] or offered limited qubit measurements by exploiting a HEMT amplifier prior to the RX [1]. Those issues hinder future monolithic integration between solid-state qubits and readout electronics. This work advances the prior art by (1) introducing a wideband passive amplification circuit at the RX front-end to minimize the shot noise contribution of the active devices, lowering prior art TN by ~2.7x; (2) demonstrating the RX performance in an RF-reflectometry qubit readout scheme without using off-the-shelf LNA prior to the RX.

The coherent control of interacting spins in semiconductor quantum dots is of strong interest for quantum information processing and for studying quantum magnetism from the bottom up. Here we present a 2 × 4 germanium quantum dot array with full and controllable interactions between nearest-neighbour spins. As a demonstration of the level of control, we define four singlet–triplet qubits in this system and show two-axis single-qubit control of each qubit and SWAP-style two-qubit gates between all neighbouring qubit pairs, yielding average single-qubit gate fidelities of 99.49(8)–99.84(1)% and Bell state fidelities of 73(1)–90(1)%. Combining these operations, we experimentally implement a circuit designed to generate and distribute entanglement across the array. A remote Bell state with a fidelity of 75(2)% and concurrence of 22(4)% is achieved. These results highlight the potential of singlet–triplet qubits as a competing platform for quantum computing and indicate that scaling up the control of quantum dot spins in extended bilinear arrays can be feasible.

Direct interactions between quantum particles naturally fall off with distance. However, future quantum computing architectures are likely to require interaction mechanisms between qubits across a range of length scales. In this work, we demonstrate a coherent interaction between two semiconductor spin qubits 250 μm apart using a superconducting resonator. This separation is several orders of magnitude larger than for the commonly used direct interaction mechanisms in this platform. We operate the system in a regime in which the resonator mediates a spin–spin coupling through virtual photons. We report the anti-phase oscillations of the populations of the two spins with controllable frequency. The observations are consistent with iSWAP oscillations of the spin qubits, and suggest that entangling operations are possible in 10 ns. These results hold promise for scalable networks of spin qubit modules on a chip.

In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This article introduces a theoretical framework to evaluate the effect of various parameters, such as the readout probe power, readout chain's noise performance, and integration time on the intrinsic readout signal-to-noise ratio, and thus readout fidelity of RF gate-based readout systems. By analyzing the underlying physics of spin qubits during readout, this work proposes a qubit readout model that takes into account the qubit's quantum mechanical properties, providing a way to evaluate the tradeoffs among the aforementioned parameters. The validity of the proposed model is evaluated by comparing the simulation and experimental results. The proposed analytical approach, the developed model, and the experimental results enable designers to optimize the entire readout chain effectively, thus leading to a faster, lower power readout system with integrated cryogenic electronics.

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 10⁵ cm² V⁻¹ s⁻¹ and low percolation density of 6.9(1) × 10¹⁰ cm⁻². These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz^−1/2 and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.

Quantum systems with engineered Hamiltonians can be used to study many-body physics problems to provide insights beyond the capabilities of classical computers. Semiconductor gate-defined quantum dot arrays have emerged as a versatile platform for realizing generalized Fermi-Hubbard physics, one of the richest playgrounds in condensed matter physics. In this work, we employ a germanium 4×2 quantum dot array and show that the naturally occurring long-range Coulomb interaction can lead to exciton formation and transport. We tune the quantum dot ladder into two capacitively coupled channels and exploit Coulomb drag to probe the binding of electrons and holes. Specifically, we shuttle an electron through one leg of the ladder and observe that a hole is dragged along in the second leg under the right conditions. This corresponds to a transition from single-electron transport in one leg to exciton transport along the ladder. Our work paves the way for the study of excitonic states of matter in quantum dot arrays.

The small footprint of semiconductor qubits is favorable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in the gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2 × 2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.

We report observations of transitions between excited states in the Jaynes-Cummings ladder of circuit quantum electrodynamics with electron spins (spin circuit QED). We show that unexplained features in recent experimental work correspond to such transitions and present an input-output framework that includes these effects. In new experiments, we first reproduce previous observations and then reveal both excited-state transitions and multiphoton transitions by increasing the probe power and using two-tone spectroscopy. This ability to probe the Jaynes-Cummings ladder is enabled by improvements in the coupling-to-decoherence ratio, and shows an increase in the maturity of spin circuit QED as an interesting platform for studying quantum phenomena.

Semiconductor spin qubits demonstrated single-qubit gates with fidelities up to 99.9 % benchmarked in the single-qubit subspace. However, tomographic characterizations reveal non-negligible crosstalk errors in a larger space. Additionally, it was long thought that the two-qubit gate performance is limited by charge noise, which couples to the qubits via the exchange interaction. Here, we show that coherent error sources such as a limited bandwidth of the control signals, diabaticity errors, microwave crosstalk, and non-linear transfer functions can equally limit the fidelity. We report a simple theoretical framework for pulse optimization that relates erroneous dynamics to spectral concentration problems and allows for the reuse of existing signal shaping methods on a larger set of gate operations. We apply this framework to common gate operations for spin qubits and show that simple pulse shaping techniques can significantly improve the performance of these gate operations in the presence of such coherent error sources. The methods presented in the paper were used to demonstrate two-qubit gate fidelities with F > 99.5 % in Xue et al (2022 Nature 601 343). We also find that single and two-qubit gates can be optimized using the same pulse shape. We use analytic derivations and numerical simulations to arrive at predicted gate fidelities greater than 99.9% with duration less than, 4 / ( Δ E z ) where Δ E z is the difference in qubit frequencies.

Coherent links between qubits separated by tens of micrometers are expected to facilitate scalable quantum computing architectures for spin qubits in electrically defined quantum dots. These links create space for classical on-chip control electronics between qubit arrays, which can help to alleviate the so-called wiring bottleneck. A promising method of achieving coherent links between distant spin qubits consists of shuttling the spin through an array of quantum dots. Here, we use a linear array of four tunnel-coupled quantum dots in a 28Si/SiGe heterostructure to create a short quantum link. We move an electron spin through the quantum dot array by adjusting the electrochemical potential for each quantum dot sequentially. By pulsing the gates repeatedly, we shuttle an electron forward and backward through the array up to 250 times, which corresponds to a total distance of approximately 80μm. We make an estimate of the spin-flip probability per hop in these experiments and conclude that this is well below 0.01% per hop.

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a ²⁸Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick ²⁸Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz^½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

Semiconductor spin qubits have gained increasing attention as a possible platform to host a fault-tolerant quantum computer. First demonstrations of spin qubit arrays have been shown in a wide variety of semiconductor materials. The highest performance for spin qubit logic has been realized in silicon, but scaling silicon quantum dot arrays in two dimensions has proven to be challenging. By taking advantage of high-quality heterostructures and carefully designed gate patterns, we are able to form a tunnel coupled 2 × 2 quantum dot array in a ²⁸Si/SiGe heterostructure. We are able to load a single electron in all four quantum dots, thus reaching the (1,1,1,1) charge state. Furthermore, we characterize and control the tunnel coupling between all pairs of dots by measuring polarization lines over a wide range of barrier gate voltages. Tunnel couplings can be tuned from about 30 μ eV up to approximately 400 μ eV . These experiments provide insightful information on how to design 2D quantum dot arrays and constitute a first step toward the operation of spin qubits in ²⁸Si/SiGe quantum dots in two dimensions.

Micromagnet-based electric dipole spin resonance offers an attractive path for the near-term scaling of dense arrays of silicon spin qubits in gate-defined quantum dots while maintaining long coherence times and high control fidelities. However, accurately controlling dense arrays of qubits using a multiplexed drive will require an understanding of the cross-talk mechanisms that may reduce operational fidelity. We identify an unexpected cross-talk mechanism whereby the Rabi frequency of a driven qubit is drastically changed when the drive of an adjacent qubit is turned on. These observations raise important considerations for scaling single-qubit control.

As spin-based quantum processors grow in size and complexity, maintaining high fidelities and minimizing crosstalk will be essential for the successful implementation of quantum algorithms and error-correction protocols. In particular, recent experiments have highlighted pernicious transient qubit frequency shifts associated with microwave qubit driving. Work-Arounds for small devices, including prepulsing with an off-resonant microwave burst to bring a device to a steady state, wait times prior to measurement, and qubit-specific calibrations all bode ill for device scalability. Here, we make substantial progress in understanding and overcoming this effect. We report a surprising nonmonotonic relation between mixing chamber temperature and spin Larmor frequency which is consistent with observed frequency shifts induced by microwave and baseband control signals. We find that purposefully operating the device at 200 mK greatly suppresses the adverse heating effect while not compromising qubit coherence or single-qubit fidelity benchmarks. Furthermore, systematic non-Markovian crosstalk is greatly reduced. Our results provide a straightforward means of improving the quality of multispin control while simplifying calibration procedures for future spin-based quantum processors.

One of the main bottlenecks in the pursuit of a large-scale-chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional array with about 12μm pitch, we create space to implement locally integrated sample-and-hold circuits. This allows us to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling, leading to a Rent's exponent as low as p=0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit array. This work presents a complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and identifying remaining challenges for achieving full fault-tolerant quantum computation. It thereby significantly closes the gap towards a fully CMOS-compatible quantum computer implementation.