Micromagnet-enabled electric-dipole spin resonance (EDSR) is an established method for high-fidelity single-spin control in silicon, although so far experiments have been restricted to one-dimensional arrays. In contrast, qubit control based on hopping spins has recently emerged as a compelling alternative, with high-fidelity baseband control realized in sparse two-dimensional hole arrays in germanium. In this work, we commission a ²⁸Si/SiGe 2 × 2 quantum dot array both as a four-qubit device using EDSR and as a two-qubit device using baseband hopping control. We establish a lower bound on the fidelity of the hopping gate of 99.50(6)%, which is similar to the average fidelity of the resonant gate. The hopping gate also circumvents the transient pulse-induced resonance shift from heating observed during EDSR operation. To motivate hopping spins as an attractive means of scaling silicon spin-qubit arrays, we propose an extensible nanomagnet design that enables engineered baseband control of large spin arrays.

Solid-state qubits are sensitive to their microscopic environment, causing the qubit properties to fluctuate on a wide range of timescales. The sub-Hz end of the spectrum is usually dealt with by repeated background calibrations, which bring considerable overhead. It is thus important to characterize and understand the low-frequency variations of the relevant qubit characteristics. In this study, we investigate the stability of spin qubit frequencies in the Si/SiGe quantum dot platform. We find that the calibrated qubit frequencies of a six-qubit device vary by up to ±100 MHz while performing a variety of experiments over a span of 912 days. These variations are sensitive to the precise voltage settings of the gate electrodes, however when these are kept constant to within 15 µV, the qubit frequencies vary by less than ±7 MHz over periods up to 36 days. During overnight scans, the qubit frequencies of ten qubits across two different devices show a standard deviation below 200 kHz within a 1-hour time window. The qubit frequency noise spectral density shows roughly a 1/f trend above 10⁻⁴ Hz and, strikingly, a steeper trend at even lower frequencies.

The small footprint of semiconductor qubits is favorable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in the gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2 × 2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.

Semiconductor spin qubits have gained increasing attention as a possible platform to host a fault-tolerant quantum computer. First demonstrations of spin qubit arrays have been shown in a wide variety of semiconductor materials. The highest performance for spin qubit logic has been realized in silicon, but scaling silicon quantum dot arrays in two dimensions has proven to be challenging. By taking advantage of high-quality heterostructures and carefully designed gate patterns, we are able to form a tunnel coupled 2 × 2 quantum dot array in a ²⁸Si/SiGe heterostructure. We are able to load a single electron in all four quantum dots, thus reaching the (1,1,1,1) charge state. Furthermore, we characterize and control the tunnel coupling between all pairs of dots by measuring polarization lines over a wide range of barrier gate voltages. Tunnel couplings can be tuned from about 30 μ eV up to approximately 400 μ eV . These experiments provide insightful information on how to design 2D quantum dot arrays and constitute a first step toward the operation of spin qubits in ²⁸Si/SiGe quantum dots in two dimensions.

Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors, and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments.