One of the main components used in superconducting quantum chips is the Josephson junction. Currently when fabricating Josephson junctions, the resistance uniformity at wafer-scale is not optimal. It is also known that an annealing process can alter the junction resistance and with it the qubit frequency. However, laser annealing has only shown to be able to increase the junction resistance. An equally effective and minimally invasive technique to decrease junction resistance is necessary to have full control on frequency targeting. Thermal annealing in a reducing environment is known to result in a global decrease in junction resistance. To get better control on frequency targeting the techniques could be combined. A die containing not-capped Manhattan type Josephson junctions has been annealed using forming gas at 200°C for 2 minutes, based on a non-linear least squares reciprocal function fit to the data an asymptotic lower bound of 467 μSμm-2 for the change in conductance per unit area has been found. Smaller junctions with an area of approximately 0.03 μm2 undergo a bigger change in conductance per unit area of around 800 μSμm-2. Annealing at higher temperatures such as 300 and 400°C results in a decrease of the conductance. There is no substantial change in yield of usable SQUIDs when using a rapid thermal annealing process.

Spin qubits in silicon have emerged as a promising candidate for a scalable quantum computer due to their small footprint, long coherence times, and their compatibility with advanced semiconductor manufacturing. However, all known spin qubit material hosts come with specific challenges, that limit the performance of quantum information processing. In this thesis we study Si/SiGe heterostructures, comprising a strained silicon (Si) quantum well which is sandwiched between two silicon-germanium (SiGe) barriers. Si/SiGe heterostructures designed to act as solid-state matrix to host spin qubits have three intrinsic material challenges that limit performance: hyperfine interaction, valley splitting, and charge noise. Therefore, to realize a scalable quantum computer in Si/SiGe heterostructures we first quantify the performance limiting parameters and subsequently, we improve them systematically with statistical significance. Acquiring data with statistical significance, however proves challenging for quantum devices in Si/SiGe heterostructures due to complicated and time-consuming fabrication schemes for device manufacturing, and the need of using dilution refrigerators that cool samples down to sub-Kelvin temperatures with only a limited amount of wires for electrical characterization of devices. Therefore, in this thesis we demonstrate fast growth-fabrication-measurement feedback cycles to accelerate our understanding on the materials and devices. We realize such fast feedback cycles by first establishing a unique workflow at TU Delft, allowing 100~mm wafer growth and fabrication. Subsequently in our first experiment, we overcome the wiring bottleneck by presenting a cryogenic multiplexing platform that multiplies DC wires inside of a dilution refrigerator. This cryogenic multiplexer platform uses commercially available CMOS components, is compatible with any dilution refrigerator, and allows us to measure thirteen chips in the same cooldown at a temperature of 50~mK and at magnetic fields of up to 10~T. We confirm these extreme measurement conditions by showing statistically significant quantum transport properties of industrially grown 300~mm $^{ ext{nat}}$Si/SiGe wafers. In the following experimental chapters we then leverage the cryogenic multiplexer to successively tackle the performance limiting parameters of spin qubit processors in Si/SiGe heterostructures. In the second experiment we first analyze valley splitting in two dimensional electron gases and observe that valley splitting increases linearly with the electric field at the quantum Hall edge states of the device at a rate consistent with theoretical predictions. In turn, this observation allows us to evaluate valley splitting on a micron length scale with relatively simple Hall-bar measurements. In the third experiment we show two major improvements in our heterostructures. First, we measure valley splitting in quantum dots with varying quantum well interface sharpness with statistical significance. We then proceed to analyze the atomic composition of the quantum well interfaces in several samples using atom probe tomography and show that Ge atoms are distributed randomly in each atomic layer. Subsequently using the atom probe tomography results as input, we simulate valley splitting and show that valley splitting depends on the atomistic details of the interface and needs to be treated as a statistical distribution. We then propose a strategy to increase valley splitting on average above a chosen threshold by introducing a small concentration of Ge atoms into the quantum well. Second, all electrical measurements in this experiment are performed in isotopically purified $^{28}$Si quantum wells, which reduces the hyperfine interaction and hence increases qubit coherence times. While we do not explicitly discuss this improvement in this chapter, it is a crucial baseline for all following experiments in this thesis and for all qubit experiments using Delft grown $^{28}$Si/SiGe heterostructures. We then move to show wafer-scale improvements of the disorder landscape of Si quantum wells in our fourth experiment. There, we challenge the common approach of growing an epitaxial Si cap on the $^{28}$Si/SiGe heterostructure, by replacing the Si cap with an amorphous Si-rich layer. We compare these two heterostructues by monitoring the statistical performance of mobility, percolation density, maximum electric field before hysteresis, and single particle relaxation time and observe a statistical performance increase of the mean value and the standard deviation. In the fifth experiment we study a heterostructure with a thin quantum well and compare its statistical performance of mobility, percolation density, and charge noise with the performance of the heterostructures from the preceding experiment. Importantly, we find that misfit dislocation arising from strain relaxation are significantly reduced in thin quantum wells as confirmed by geometrical phase analysis of transmission-electron microscope images. In consequence, we observe a statistical performance increase of all key metrics in the novel heterostructure, only possible by our approach of engineering the critical material layers. Finally, we see promising simulated qubit coherence times and qubit error rates when using our charge noise results as simulation input, hinting at a practical advantage of our novel $^{28}$Si/SiGe heterostructures for quantum processors. In the last experimental chapter we demonstrate how our improved $^{28}$Si/SiGe heterostructures have enabled two key experiments in the field of spin-based quantum computing. First, we show that our purified heterostrucures may host high-quality qubits, that in turn serve as a testbed for demonstrating CMOS-based cryogenic control of silicon quantum circuits. Second, we show how our isotopically purified, low-disorder heterostructures host a 6-qubit quantum processor with high-fidelity initialization, high-fidelity gate operation, and high-fidelity readout. We conclude this thesis by highlighting key improvements of our $^{28}$Si/SiGe hetero-structures that have contributed to state-of-the-art spin qubit experiments. However, our heterostructures still require further improvements if we want to achieve error rates around 10$^{-6}$ and scale to large spin qubit arrays with more than a million qubits. Therefore, we discuss additional material changes that could further lower spin qubit error rates and we consider how to assess the uniformity of the material over different length scales, relevant when striving for larger qubit arrays. @en

This dissertation describes a set of experiments with the goal of creating a super-conductor-semiconductor hybrid circuit quantum electrodynamics architecture with single electron spins. Single spins in silicon quantum dots have emerged as attractive qubits for quantum computation. However, how to scale up spin qubit systems remains an open question. The hybrid architecture considered here could provide a route to realizing large networks of quantum dot–based spin qubit registers. The first experiment in this thesis is aimed at achieving strong coupling between a single electron spin and a single microwave photon. The electron is trapped in a gate-defined double quantum dot in a Si/SiGe heterostructure and the photon is stored in an on-chip superconducting high-impedance NbTiN cavity. The photon is coupled directly to the electron charge, and indirectly to the electron spin, mediated through a synthetic spin-orbit field. We observe a vacuum Rabi splitting that depends on the spin-charge hybridization. The ratio of spin-photon coupling strength to decoherence rates of the spin and cavity combined is larger than unity, confirming the strong coupling regime has been reached. In addition, we find an optimal degree of spin-charge hybridization for which this ratio is maximized. The demonstration of strong spin-photon coupling not only opens a new range of physics experiments, but fulfills also a crucial requirement for coupling spin qubits at a distance via a cavity. The second experiment is focused on spin readout with the on-chip cavity. Instead of the direct dispersive readout of a single spin, we use the cavity to detect whether the electron is allowed to tunnel between the two dots or not. We benchmark the charge sensitivity and bandwidth of the detector and find that rapid detection of the electron charge with high SNR is possible. In the two-electron regime, electron tunneling is contingent on the total spin state (Pauli spin blockade). This spin-to-charge conversion scheme enables single-shot detection of singlet states with high-fidelity. The demonstration of single-shot spin readout with a cavity is an essential step towards readout in dense spin qubit arrays, such as the crossbar network, where it is not possible to integrate electrometers and accompanying reservoirs adjacent to the qubit dots. In the third experiment, we develop on-chip microwave filters to suppress microwave photon leakage from the cavity through the gate electrodes that are necessary to form quantum dots. We introduce a new cavity design that is compatible with long-distance connectivity between spins, but is also more susceptible to microwave leakage. We test and compare two low-pass filter variations in terms of performance, footprint and integrability. They use the same nanowire inductor, but different implementations of the capacitor: one with a planar interdigitated capacitor and one novel design with an overlapping thin-film capacitor. We find that both approaches are effective against microwave leakage. However, the large footprint of the interdigitated capacitor makes this solution inconvenient as the number of gate lines increases. The thin-film capacitor, with its much smaller footprint, is better suited for our devices. The final part of this dissertation contains concluding remarks and possible future directions are proposed. @en

Quantum computers based on semiconductor quantum dots are proving promising contenders for large scale quantum information processing. In particular, group IV based semiconductor hosts containing an abundance of nuclear spin-zero isotopes have made considerable headway into fulfilling the requirements of a universal quantum computer. Silicon (Si) and germanium (Ge) are two elements that have played important roles in the history of classical computing, and are now poised to do the same in the future of quantum computation. In this thesis, we advance efforts in developing a quantum computer in both Si, using electron spins in Si-metaloxide- semiconductor (SiMOS) hosted quantum dots, and hole spins in planar germanium quantumwells (Ge/SiGe). @en